Issued Patents All Time
Showing 26–50 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8447888 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2013-05-21 |
| 8402222 | Caching for heterogeneous processors | Frank T. Hady, Mason Cabot, John Beck | 2013-03-19 |
| 8380923 | Queue arrays in network devices | Gilbert M. Wolrich, Debra Bernstein | 2013-02-19 |
| 8230119 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2012-07-24 |
| 8230120 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2012-07-24 |
| 8156285 | Heterogeneous processors sharing a common cache | Frank T. Hady, Mason Cabot, John Beck | 2012-04-10 |
| 8099523 | PCI express enhancements and extensions including transactions having prefetch parameters | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2012-01-17 |
| 8073981 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2011-12-06 |
| 7949794 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2011-05-24 |
| 7930566 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2011-04-19 |
| 7899943 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more | 2011-03-01 |
| 7895239 | Queue arrays in network devices | Gilbert M. Wolrich, Debra Bernstein | 2011-02-22 |
| 7853951 | Lock sequencing to reorder and grant lock requests from multiple program threads | Sanjeev Kumar Jain, Gilbert M. Wolrich | 2010-12-14 |
| 7769026 | Efficient sort scheme for a hierarchical scheduler | Sanjeev Kumar Jain, Gilbert M. Wolrich | 2010-08-03 |
| 7707266 | Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit | Sridhar Lakshmanamurthy, Matthew J. Adiletta, Jeen-Xuan Miin, Bijoy Bose | 2010-04-27 |
| 7689867 | Multiprocessor breakpoint | Xiao-Feng Li, Dz-ching Ju, Aaron Kunze | 2010-03-30 |
| 7684970 | Graphical user interface for use during processor simulation | Donald F. Hooper, Eric Walker, Dennis Laurier Rivard | 2010-03-23 |
| 7650558 | Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systems | Pete D. Vogt | 2010-01-19 |
| 7610451 | Data transfer mechanism using unidirectional pull bus and push bus | Gilbert M. Wolrich, Debra Bernstein, Matthew J. Adiletta | 2009-10-27 |
| 7577792 | Heterogeneous processors sharing a common cache | Frank T. Hady, Mason Cabot, John Beck | 2009-08-18 |
| 7555630 | Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit | Sanjeev Kumar Jain, Gilbert M. Wolrich | 2009-06-30 |
| 7554908 | Techniques to manage flow control | Sanjeev Kumar Jain, Gilbert M. Wolrich, Hugh Wilkinson | 2009-06-30 |
| 7512729 | Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency | Bijoy Bose, Sridhar Lakshmanamurthy, Irwin Vaz, Suri B. Medapati, Edwin O'Yang | 2009-03-31 |
| 7487505 | Multithreaded microprocessor with register allocation based on number of active threads | Gilbert M. Wolrich, Debra Bernstein | 2009-02-03 |
| 7443836 | Processing a data packet | Donald F. Hooper, Gilbert M. Wolrich, Matthew J. Adiletta, Hugh Wilkinson, Robert J. Kushlis | 2008-10-28 |