MR

Mark Rosenbluth

IN Intel: 78 patents #320 of 30,777Top 2%
NV NVIDIA: 9 patents #816 of 7,811Top 15%
DE Digital Equipment: 1 patents #1,005 of 2,100Top 50%
TI Tilera: 1 patents #19 of 28Top 70%
📍 Uxbridge, MA: #1 of 121 inventorsTop 1%
🗺 Massachusetts: #328 of 88,656 inventorsTop 1%
Overall (All Time): #18,173 of 4,157,543Top 1%
89
Patents All Time

Issued Patents All Time

Showing 76–89 of 89 patents

Patent #TitleCo-InventorsDate
7185153 Packet assembly Prashant R. Chandra, Sridhar Lakshmanamurthy, Chen-Chi Kuo, Rohit Natarajan 2007-02-27
7181594 Context pipelines Hugh Wilkinson, Matthew J. Adiletta, Debra Bernstein, Gilbert M. Wolrich 2007-02-20
7181573 Queue array caching in network devices Gilbert M. Wolrich, Debra Bernstein 2007-02-20
7181568 Content addressable memory to identify subtag matches Gilbert M. Wolrich 2007-02-20
7158964 Queue management Gilbert M. Wolrich, Debra Bernstein, Donald F. Hooper 2007-01-02
7149226 Processing data packets Gilbert M. Wolrich, Debra Bernstein 2006-12-12
7107413 Write queue descriptor count instruction for high speed queuing Debra Bernstein, Gilbert M. Wolrich 2006-09-12
6973550 Memory access control Gilbert M. Wolrich, Debra Bernstein, Richard Guerin 2005-12-06
6941438 Memory interleaving Gilbert M. Wolrich 2005-09-06
6934951 Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section Hugh Wilkinson, Matthew J. Adiletta, Gilbert M. Wolrich, Debra Bernstein, Myles Wilde 2005-08-23
6868476 Software controlled content addressable memory in a general purpose execution datapath Gilbert M. Wolrich, Debra Bernstein 2005-03-15
6779084 Enqueue operations for multi-buffer packets Gilbert M. Wolrich, Debra Bernstein 2004-08-17
6738831 Command ordering Gilbert M. Wolrich, Debra Bernstein, Richard Guerin 2004-05-18
5553270 Apparatus for providing improved memory access in page mode access systems with pipelined cache access and main memory address replay 1996-09-03