Issued Patents All Time
Showing 51–75 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7441245 | Phasing for a multi-threaded network processor | Donald F. Hooper, Debra Bernstein, Michael F. Fallon, Sanjeev Kumar Jain, Gilbert M. Wolrich | 2008-10-21 |
| 7437724 | Registers for data transfers | Gilbert M. Wolrich, Debra Bernstein, Matthew J. Adiletta, Hugh Wilkinson | 2008-10-14 |
| 7437510 | Instruction-assisted cache management for efficient use of cache and memory | Sridhar Lakshmanamurthy | 2008-10-14 |
| 7418571 | Memory interleaving | Gilbert M. Wolrich, Matthew J. Adiletta | 2008-08-26 |
| 7412584 | Data alignment micro-architecture systems and methods | Jose Niell, Gilbert M. Wolrich, Thomas L. Dmukauskas | 2008-08-12 |
| 7412551 | Methods and apparatus for supporting programmable burst management schemes on pipelined buses | Bijoy Bose, Irwin Vaz, Sridhar Lakshmanamurthy | 2008-08-12 |
| 7401184 | Matching memory transactions to cache line boundaries | Mason Cabot, Frank T. Hady | 2008-07-15 |
| 7376950 | Signal aggregation | Gilbert M. Wolrich, Debra Bernstein, Myles Wilde | 2008-05-20 |
| 7360031 | Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces | Sridhar Lakshmanamurthy, Mason Cabot, Sameer Nanavati | 2008-04-15 |
| 7337275 | Free list and ring data structure management | Gilbert M. Wolrich, Debra Bernstein, John Sweeney, James D. Guilford | 2008-02-26 |
| 7325099 | Method and apparatus to enable DRAM to support low-latency access via vertical caching | Sanjeev Kumar Jain, Matthew J. Adiletta, Gilbert M. Wolrich | 2008-01-29 |
| 7324520 | Method and apparatus to process switch traffic | Sridhar Lakshmanamurthy, Lawrence B. Huston, III, Debra Bernstein, Hugh Wilkinson | 2008-01-29 |
| 7313140 | Method and apparatus to assemble data segments into full packets for efficient packet-based classification | Sridhar Lakshmanamurthy, Charles E. Narad, Lawrence B. Huston, III, Yim Pun, Raymond Ng +1 more | 2007-12-25 |
| 7302549 | Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access | Hugh Wilkinson, Matthew J. Adiletta, Gilbert M. Wolrich, Debra Bernstein, Myles Wilde | 2007-11-27 |
| 7302528 | Caching bypass | Mason Cabot, Frank T. Hady, David Tennenhouse | 2007-11-27 |
| 7269179 | Control mechanisms for enqueue and dequeue operations in a pipelined network processor | Gilbert M. Wolrich, Debra Bernstein, Matthew J. Adiletta | 2007-09-11 |
| 7257665 | Branch-aware FIFO for interprocessor data sharing | Jose Niell | 2007-08-14 |
| 7251219 | Method and apparatus to communicate flow control information in a duplex network processor system | Sridhar Lakshmanamurthy, Lawrence B. Huston, III, Yim Pun, Raymond Ng, Hugh Wilkinson +1 more | 2007-07-31 |
| 7246197 | Software controlled content addressable memory in a general purpose execution datapath | Gilbert M. Wolrich, Debra Bernstein | 2007-07-17 |
| 7240164 | Folding for a multi-threaded network processor | Donald F. Hooper, Hugh Wilkinson, Debra Bernstein, Michael F. Fallon, Sanjeev Kumar Jain +2 more | 2007-07-03 |
| 7225281 | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms | Gilbert M. Wolrich, Debra Bernstein, Myles Wilde, Matthew J. Adiletta | 2007-05-29 |
| 7216204 | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment | Gilbert M. Wolrich, Debra Bernstein | 2007-05-08 |
| 7210008 | Memory controller for padding and stripping data in response to read and write commands | Prashant R. Chandra, Sridhar Lakshmanamurthy, Chen-Chi Kuo, Rohit Natarajan | 2007-04-24 |
| 7200713 | Method of implementing off-chip cache memory in dual-use SRAM memory for network processors | Mason Cabot, Frank T. Hady | 2007-04-03 |
| 7200699 | Scalable, two-stage round robin arbiter with re-circulation and bounded latency | Bijoy Bose, Sridhar Lakshmanamurthy, Irwin Vaz, Alok Mathur | 2007-04-03 |