Issued Patents All Time
Showing 76–100 of 212 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7859304 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Yan Chong, Bonnie I. Wang | 2010-12-28 |
| 7746134 | Digitally controlled delay-locked loops | Sean Shau-Tu Lu, Chiakang Sung, Yan Chong | 2010-06-29 |
| 7725755 | Self-compensating delay chain for multiple-date-rate interfaces | Yan Chong, Chiakang Sung, Bonnie I. Wang, Xiaobao Wang, Philip Pan +1 more | 2010-05-25 |
| 7710149 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Chiakang Sung, Bonnie I. Wang +5 more | 2010-05-04 |
| 7706996 | Write-side calibration for data interface | Yan Chong, Chiakang Sung, Michael H. M. Chu | 2010-04-27 |
| 7702978 | Soft error location and sensitivity detection for programmable devices | David Lewis, Ninh D. Ngo, Andy L. Lee | 2010-04-20 |
| 7671579 | Method and apparatus for quantifying and minimizing skew between signals | Yan Chong, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2010-03-02 |
| 7642812 | Distribution and synchronization of a divided clock signal | Ning Xue, Philip Clarke, Yan Chong | 2010-01-05 |
| 7593273 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke +1 more | 2009-09-22 |
| 7590879 | Clock edge de-skew | Henry Kim, Bonnie I. Wang, Chiakang Sung | 2009-09-15 |
| 7590008 | PVT compensated auto-calibration scheme for DDR3 | Manoj B. Roge, Andrew Bellis, Philip Clarke, Michael H. M. Chu, Yan Chong | 2009-09-15 |
| 7589556 | Dynamic control of memory interface timing | Johnson Tan, Andrew Bellis, Philip Clarke, Yan Chong, Michael H. M. Chu +1 more | 2009-09-15 |
| 7586341 | Programmable high-speed interface | Bonnie Wang, Chiakang Sung, Khai Nguyen, Philip Pan | 2009-09-08 |
| 7535275 | High-performance memory interface circuit architecture | Chiakang Sung, Philip Pan, Yan Chong, Andy L. Lee, Brian Johnson | 2009-05-19 |
| 7509223 | Read-side calibration for data interface | Yan Chong, Chiakang Sung, Michael H. M. Chu | 2009-03-24 |
| 7503780 | USB flash disk with cover | — | 2009-03-17 |
| 7492185 | Innovated technique to reduce memory interface write mode SSN in FPGA | Chiakang Sung, Michael H. M. Chu, Yan Chong | 2009-02-17 |
| 7477074 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Yan Chong, Bonnie I. Wang | 2009-01-13 |
| 7425844 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Chiakang Sung, Bonnie I. Wang +5 more | 2008-09-16 |
| 7358783 | Voltage, temperature, and process independent programmable phase shift for PLL | Bonnie I. Wang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung +1 more | 2008-04-15 |
| 7330051 | Innovated technique to reduce memory interface write mode SSN in FPGA | Chiakang Sung, Michael H. M. Chu, Yan Chong | 2008-02-12 |
| 7324405 | DQS postamble filtering | Sanjay K. Charagulla, Chiakang Sung, Bonnie I. Wang, Yan Chong | 2008-01-29 |
| 7321518 | Apparatus and methods for providing redundancy in integrated circuits | Chiakang Sung, Philip Pan, Yan Chong | 2008-01-22 |
| 7315188 | Programmable high speed interface | Bonnie Wang, Chiakang Sung, Khai Nguyen, Philip Pan | 2008-01-01 |
| 7231536 | Control circuit for self-compensating delay chain for multiple-data-rate interfaces | Yan Chong, Chiakang Sung, Philip Pan | 2007-06-12 |