Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7844801 | Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors | Hong Wang, Perry Wang, Jeffery A. Brown, Per Hammarlund, Doron Orenstein +2 more | 2010-11-30 |
| 7747897 | Method and apparatus for lockstep processing on a fixed-latency interconnect | Paul Racunas, Matthew Mattina, Shubhendu Sekhar Mukherjee | 2010-06-29 |
| 7733898 | Method and apparatus for preventing starvation in a slotted-ring network | Matthew Mattina, Yungho Choi | 2010-06-08 |
| 7710904 | Ring network with variable token activation | — | 2010-05-04 |
| 7689844 | Credit-based activity regulation within a microprocessor based on an accumulative credit system | — | 2010-03-30 |
| 7624236 | Predictive early write-back of owned cache blocks in a shared memory computer system | Matthew Mattina | 2009-11-24 |
| 7607048 | Method and apparatus for protecting TLB's VPN from soft errors | Ugonna Echeruo, John H. Crawford, Shubhendu Sekhar Mukherjee | 2009-10-20 |
| 7539141 | Method and apparatus for synchronous unbuffered flow control of packets on a ring interconnect | Matthew Mattina, Stephen Felix | 2009-05-26 |
| 7353414 | Credit-based activity regulation within a microprocessor based on an allowable activity level | — | 2008-04-01 |
| 7003648 | Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU | Chuan-Hua Chang, Joel S. Emer, John H. Mylius, Peter G. Soderquist | 2006-02-21 |
| 6549930 | Method for scheduling threads in a multithreaded processor | Jeffrey Adgate Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl | 2003-04-15 |
| 6470443 | Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information | Joel S. Emer, Rebecca L. Stamm, Trggve Fossum, Robert H. Halstead, Jr., Dean Tullsen +2 more | 2002-10-22 |
| 6374367 | Apparatus and method for monitoring a computer system to guide optimization | Jeffrey Adgate Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl | 2002-04-16 |
| 6324616 | Dynamically inhibiting competing resource requesters in favor of above threshold usage requester to reduce response delay | Wilson P. Snyder, II | 2001-11-27 |
| 6233645 | Dynamically disabling speculative prefetch when high priority demand fetch opportunity use is high | Wilson P. Snyder, II | 2001-05-15 |
| 6195748 | Apparatus for sampling instruction execution information in a processor pipeline | Jeffrey Adgate Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl, Daniel Leibholz +1 more | 2001-02-27 |
| 6175814 | Apparatus for determining the instantaneous average number of instructions processed | Jeffrey Adgate Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl | 2001-01-16 |
| 6163840 | Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline | Jeffrey Adgate Dean, James E. Hicks, Daniel Leibholz, Edward J. McLellan, Carl A. Waldspurger +1 more | 2000-12-19 |
| 6148396 | Apparatus for sampling path history in a processor pipeline | Jeffrey Adgate Dean, Robert Alan Eustace, James E. Hicks, Carl A. Waldspurger, William E. Weihl | 2000-11-14 |
| 6108770 | Method and apparatus for predicting memory dependence using store sets | Joel S. Emer, Bruce E. Edwards, John H. Edmondson | 2000-08-22 |
| 6073159 | Thread properties attribute vector based thread selection in multithreading processor | Joel S. Emer, Rebecca L. Stamm, Trggve Fossum, Robert H. Halstead, Jr., Dean Tullsen +2 more | 2000-06-06 |
| 6000044 | Apparatus for randomly sampling instructions in a processor pipeline | Jeffrey Adgate Dean, James E. Hicks, Daniel Leibholz, Edward J. McLellan, Carl A. Waldspurger +1 more | 1999-12-07 |
| 5923872 | Apparatus for sampling instruction operand or result values in a processor pipeline | Jeffrey Adgate Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl | 1999-07-13 |
| 5809450 | Method for estimating statistics of properties of instructions processed by a processor pipeline | Jeffrey Adgate Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl | 1998-09-15 |