Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6625717 | Single cycle linear address calculation for relative branch addressing | Jonathan P. Douglas | 2003-09-23 |
| 6594734 | Method and apparatus for self modifying code detection using a translation lookaside buffer | Chan Woo Lee, Vihang D. Pandya, Roshan Fernando | 2003-07-15 |
| 6591344 | Method and system for an INUSE field resource management scheme | Darrell D. Boggs | 2003-07-08 |
| 6578138 | System and method for unrolling loops in a trace cache | Robert F. Krick | 2003-06-10 |
| 6564298 | Front end system having multiple decoding modes | Stephan Jourdan | 2003-05-13 |
| 6535905 | Method and apparatus for thread switching within a multithreaded processor | Stavros Kalafatis, Robert D. Fisch | 2003-03-18 |
| 6502177 | Single cycle linear address calculation for relative branch addressing | Jonathan P. Douglas | 2002-12-31 |
| 6493821 | Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table | Reynold V. D'Sa, Robert F. Krick, Rebecca E. Hebda | 2002-12-10 |
| 6467027 | Method and system for an INUSE field resource management scheme | Darrell D. Boggs | 2002-10-15 |
| 6374350 | System and method of maintaining and utilizing multiple return stack buffers | Reynold V. D'Sa, Rebecca E. Hebda, Stavros Kalafatis, Robert B. Chaput | 2002-04-16 |
| 6338132 | System and method for storing immediate data | Per Hammarlund, Chan Woo Lee, Robert F. Krick, Hitesh Ahuja, William C. Alexander +1 more | 2002-01-08 |
| 6308279 | Method and apparatus for power mode transition in a multi-thread processor | Bret L. Toll, Stephen H. Gunther | 2001-10-23 |
| 6151671 | System and method of maintaining and utilizing multiple return stack buffers | Reynold V. D'Sa, Rebecca E. Hebda, Stavros Kalafatis, Robert B. Chaput | 2000-11-21 |
| 6055630 | System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units | Reynold V. D'Sa, Gad Sheaffer, Gustavo P. Espinosa, Stavros Kalafatis, Rebecca E. Hebda | 2000-04-25 |
| 6041403 | Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction | Donald D. Parker, Darrell D. Boggs | 2000-03-21 |
| 6026477 | Branch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction pool | Darrell D. Boggs | 2000-02-15 |
| 5537560 | Method and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessor | Darrell D. Boggs, Scott Dion Rodgers | 1996-07-16 |