Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10332850 | Method for producing contact areas on a semiconductor substrate | Eric Beyne, Wenqi Zhang, Geraldine Jamieson | 2019-06-25 |
| 9646930 | Semiconductor device having through-substrate vias | Deniz Sabuncuoglu Tezcan, Yann Civale, Eric Beyne | 2017-05-09 |
| 8809188 | Method for fabricating through substrate vias | Deniz Sabuncuoglu Tezcan, Yann Civale, Eric Beyne | 2014-08-19 |
| 8076768 | IC interconnect | Kenneth Kaskoun, Shiqun Gu | 2011-12-13 |
| 7985620 | Method of fabricating via first plus via last IC interconnect | Kenneth Kaskoun, Shiqun Gu | 2011-07-26 |
| 7939926 | Via first plus via last technique for IC interconnects | Kenneth Kaskoun, Shiqun Gu | 2011-05-10 |
| 7795113 | Method for bonding a die or substrate to a carrier | Eric Beyne | 2010-09-14 |
| 7566634 | Method for chip singulation | Eric Beyne, Serge Vanhaelemeersch | 2009-07-28 |
| 7565219 | Lithographic apparatus, method of determining a model parameter, device manufacturing method, and device manufactured thereby | Maurits Van Der Schaar, Jeroen Huijbregstse, Sicco Ian Schets | 2009-07-21 |
| 7558643 | Lithographic apparatus, method of determining a model parameter, device manufacturing method, and device manufactured thereby | Maurits Van Der Schaar, Jeroen Huijbregtse, Sicco Ian Schets | 2009-07-07 |
| 7042552 | Alignment strategy optimization method | Roy Werkman, Franciscus Bernardus Maria Van Bilsen | 2006-05-09 |