Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9543328 | Metal oxide TFT device and method for manufacturing the same | Peng Wei, Zihong Liu | 2017-01-10 |
| 9466374 | Systems, methods, and apparatus for memory cells with common source lines | Venkatraman Prabhakar, Igor G. Kouznetsov, Long Hinh, Bo Jin | 2016-10-11 |
| 9355725 | Non-volatile memory and method of operating the same | Bo Jin, Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar | 2016-05-31 |
| 9349609 | Semiconductor process temperature optimization | Brian J. Greene, Yue Liang | 2016-05-24 |
| 9337338 | Tucked active region without dummy poly for performance boost and variation reduction | Brian J. Greene, Yue Liang | 2016-05-10 |
| 9269796 | Manufacturing method of a thin film transistor and pixel unit thereof | Peng Wei, Zihong Liu | 2016-02-23 |
| 9180223 | Biphasic osteochondral scaffold for reconstruction of articular cartilage | Paul Lee | 2015-11-10 |
| 9105722 | Tucked active region without dummy poly for performance boost and variation reduction | Brian J. Greene, Yue Liang | 2015-08-11 |
| 9082877 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon +1 more | 2015-07-14 |
| 9070459 | Erase operation control sequencing apparatus, systems, and methods | Jin-Man Han, Aaron Yip | 2015-06-30 |
| 8993389 | Dummy gate interconnect for semiconductor device | Brian J. Greene, Yue Liang | 2015-03-31 |
| 8953380 | Systems, methods, and apparatus for memory cells with common source lines | Venkatraman Prabhakar, Igor G. Kouznetsov, Long Hinh, Bo Jin | 2015-02-10 |
| 8853035 | Tucked active region without dummy poly for performance boost and variation reduction | Brian J. Greene, Yue Liang | 2014-10-07 |
| 8835234 | MOS having a sic/sige alloy stack | Dureseti Chidambarrao, Brian J. Greene, Yue Liang | 2014-09-16 |
| 8803243 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon +1 more | 2014-08-12 |
| 8785291 | Post-gate shallow trench isolation structure formation | Brian J. Greene, Yue Liang | 2014-07-22 |
| 8779469 | Post-gate shallow trench isolation structure formation | Brian J. Greene, Yue Liang | 2014-07-15 |
| 8754412 | Intra die variation monitor using through-silicon via | Anda C. Mocuta, Toshiaki Kirihata | 2014-06-17 |
| 8629022 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | Dureseti Chidambarrao, Sunfei Fang, Yue Liang, Jun Yuan | 2014-01-14 |
| 8626480 | Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors | Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta +2 more | 2014-01-07 |
| 8582390 | Wordline voltage transfer apparatus, systems, and methods | Jin-Man Han | 2013-11-12 |
| 8481397 | Polysilicon resistor and E-fuse for integration with metal gate and high-k dielectric | Roger A. Booth, Jr., Kangguo Cheng, Rainer Loesing, Chengwen Pei | 2013-07-09 |
| 8476706 | CMOS having a SiC/SiGe alloy stack | Dureseti Chidambarrao, Brian J. Greene, Yue Liang | 2013-07-02 |
| 8466496 | Selective partial gate stack for improved device isolation | Dureseti Chidambarrao, Brian J. Greene, Yue Liang | 2013-06-18 |
| 8445974 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | Dureseti Chidambarrao, Sunfei Fang, Yue Liang, Jun Yuan | 2013-05-21 |