Issued Patents All Time
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7027326 | 3T1D memory cells using gated diodes and methods of use thereof | Robert H. Dennard | 2006-04-11 |
| 6999370 | Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture | Robert H. Dennard, Stephen V. Kosonocky | 2006-02-14 |
| 6982897 | Nondestructive read, two-switch, single-charge-storage device RAM devices | Robert H. Dennard | 2006-01-03 |
| 6915004 | Continuous tomography bed motion data processing apparatus and method | Danny F. Newport, Michael E. Casey, Johnny H. Reed | 2005-07-05 |
| 6774358 | Normalization apparatus for PET and SPECT scanners and method for using same | James J. Hamill, Michael E. Casey, Timothy G. Gremillion, Stephen D. Miller | 2004-08-10 |
| 6768692 | Multiple subarray DRAM having a single shared sense amplifier | Toshiaki Kirihata | 2004-07-27 |
| 6552944 | Single bitline direct sensing architecture for high speed memory device | John A. Fifield, Toshiaki Kirihata, Jeremy K. Stephens, Daniel W. Storaska | 2003-04-22 |
| 6518827 | Sense amplifier threshold compensation | John A. Fifield, Robert H. Dennard, Russell J. Houghton, Toshiaki Kirihara | 2003-02-11 |
| 6438051 | Stabilized direct sensing memory architecture | John A. Fifield, Daniel W. Storaska | 2002-08-20 |
| 6191989 | Current sensing amplifier | William Robert Reohr, Roy E. Scheuerlein | 2001-02-20 |
| 5883814 | System-on-chip layout compilation | Wei Hwang, Yasunao Katayama | 1999-03-16 |
| 5790839 | System integration of DRAM macros and logic cores in a single chip architecture | Wei Hwang | 1998-08-04 |
| 5392221 | Procedure to minimize total power of a logic network subject to timing constraints | Wilm E. Donath, Donald T. Tang | 1995-02-21 |