Issued Patents All Time
Showing 226–250 of 414 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9618999 | Idle-aware margin adaption | Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu | 2017-04-11 |
| 9600287 | Latent modification instruction for transactional execution | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2017-03-21 |
| 9600286 | Latent modification instruction for transactional execution | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2017-03-21 |
| 9594661 | Method for executing a query instruction for idle time accumulation among cores in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2017-03-14 |
| 9594660 | Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2017-03-14 |
| 9588762 | Vector find element not equal instruction | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz | 2017-03-07 |
| 9588863 | Generation and application of stressmarks in a computer system | Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu | 2017-03-07 |
| 9588763 | Vector find element not equal instruction | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz | 2017-03-07 |
| 9582324 | Controlling execution of threads in a multi-threaded processor | Khary J. Alexander, Fadi Y. Busaba, Mark S. Farrell, John G. Rell, Jr. | 2017-02-28 |
| 9582413 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi | 2017-02-28 |
| 9575802 | Controlling execution of threads in a multi-threaded processor | Khary J. Alexander, Fadi Y. Busaba, Mark S. Farrell, John G. Rell, Jr. | 2017-02-21 |
| 9569370 | Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB) | Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi | 2017-02-14 |
| 9563467 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2017-02-07 |
| 9563468 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2017-02-07 |
| 9558032 | Conditional instruction end operation | Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt | 2017-01-31 |
| 9547523 | Conditional instruction end operation | Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt | 2017-01-17 |
| 9535608 | Memory access request for a memory protocol | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura | 2017-01-03 |
| 9529598 | Transaction abort instruction | Dan F. Greiner, Christian Jacobi, Marcel Mitran | 2016-12-27 |
| 9507602 | Sharing program interrupt logic in a multithreaded processor | Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Christian Jacobi | 2016-11-29 |
| 9507628 | Memory access request for a memory protocol | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura | 2016-11-29 |
| 9501232 | Transactional memory operations with write-only atomicity | Michael K. Gschwind, Chung-Lung K. Shum | 2016-11-22 |
| 9495108 | Transactional memory operations with write-only atomicity | Michael K. Gschwind, Chung-Lung K. Shum | 2016-11-15 |
| 9489285 | Modifying run-time-instrumentation controls from a lesser-privileged state | Mark S. Farrell, Charles W. Gainey, Jr., Chung-Lung K. Shum | 2016-11-08 |
| 9489144 | Transactional memory operations with read-only atomicity | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2016-11-08 |
| 9489142 | Transactional memory operations with read-only atomicity | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2016-11-08 |