Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7308593 | Interlocked synchronous pipeline clock gating | Hans M. Jacobson, Pradip Bose, Peter W. Cook, Stanley E. Schuster | 2007-12-11 |
| 7178120 | Method for performing timing closure on VLSI chips in a distributed environment | Nathaniel D. Hieter, David J. Hathaway, David S. Kung, Leon Stok | 2007-02-13 |
| 7100144 | System and method for topology selection to minimize leakage power during synthesis | Hans M. Jacobson, Leon Sigal | 2006-08-29 |
| 7076681 | Processor with demand-driven clock throttling power reduction | Pradip Bose, Daniel Citron, Peter W. Cook, Philip G. Emma, Hans M. Jacobson +3 more | 2006-07-11 |
| 7065665 | Interlocked synchronous pipeline clock gating | Hans M. Jacobson, Pradip Bose, Peter W. Cook, Stanley E. Schuster | 2006-06-20 |
| 7047163 | Method and apparatus for applying fine-grained transforms during placement synthesis interaction | Kanad Chakraborty, Wilm E. Donath, Lakshmi N. Reddy, Leon Stok, Andrew J. Sullivan +1 more | 2006-05-16 |
| 6946869 | Method and structure for short range leakage control in pipelined circuits | Hans M. Jacobson, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Philip G. Emma +1 more | 2005-09-20 |
| 6608771 | Low-power circuit structures and methods for content addressable memories and random access memories | Hans M. Jacobson, Stanley E. Schuster, Peter W. Cook | 2003-08-19 |
| 6512397 | Circuit structures and methods for high-speed low-power select arbitration | Hans M. Jacobson, Peter W. Cook, Stanley E. Schuster | 2003-01-28 |
| 6314547 | Method for improving the assignment of circuit locations during fabrication | Wilm E. Donath | 2001-11-06 |
| 6090153 | Multi-threshold-voltage differential cascode voltage switch (DCVS) circuits | Wei Chen, Wei Hwang | 2000-07-18 |