Issued Patents All Time
Showing 51–75 of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10727070 | Liner-less contact metallization | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2020-07-28 |
| 10692722 | Single process for linear and metal fill | Praneet Adusumilli, Alexander Reznicek, Chih-Chao Yang | 2020-06-23 |
| 10672611 | Hardmask stress, grain, and structure engineering for advanced memory applications | Michael Rizzolo, Ashim Dutta, Chih-Chao Yang | 2020-06-02 |
| 10665541 | Biconvex low resistance metal wire | Praneet Adusumilli, Alexander Reznicek | 2020-05-26 |
| 10651042 | Salicide bottom contacts | Praneet Adusumilli, Alexander Reznicek | 2020-05-12 |
| 10622406 | Dual metal nitride landing pad for MRAM devices | Alexander Reznicek, Michael Rizzolo | 2020-04-14 |
| 10600860 | Precise/designable FinFET resistor structure | Praneet Adusumilli, Shanti Pancharatnam, Alexander Reznicek | 2020-03-24 |
| 10593659 | Deep high capacity capacitor for bulk substrates | Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek | 2020-03-17 |
| 10580966 | Faceted sidewall magnetic tunnel junction structure | Alexander Reznicek, Praneet Adusumilli | 2020-03-03 |
| 10573596 | FinFET fuses formed at tight pitch dimensions | Alexander Reznicek, Praneet Adusumilli, Bahman Hekmatshoartabari | 2020-02-25 |
| 10546918 | Multilayer buried metal-insultor-metal capacitor structures | Alexander Reznicek, Joshua M. Rubin, Praneet Adusumilli | 2020-01-28 |
| 10546915 | Buried MIM capacitor structure with landing pads | Alexander Reznicek, Praneet Adusumilli, Joshua M. Rubin | 2020-01-28 |
| 10546815 | Low resistance interconnect structure with partial seed enhancement liner | Joseph F. Maniscalco, Koichi Motoyama, Alexander Reznicek | 2020-01-28 |
| 10541207 | Biconvex low resistance metal wire | Praneet Adusumilli, Alexander Reznicek | 2020-01-21 |
| 10541202 | Programmable buried antifuse | Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek | 2020-01-21 |
| 10510829 | Secondary use of aspect ratio trapping trenches as resistor structures | Alexander Reznicek, Chih-Chao Yang, Praneet Adusumilli | 2019-12-17 |
| 10461148 | Multilayer buried metal-insultor-metal capacitor structures | Alexander Reznicek, Joshua M. Rubin, Praneet Adusumilli | 2019-10-29 |
| 10446746 | ReRAM structure formed by a single process | Alexander Reznicek, Adra Carr, Praneet Adusumilli | 2019-10-15 |
| 10431542 | Low resistance seed enhancement spacers for voidless interconnect structures | Praneet Adusumilli, Joseph F. Maniscalco, Alexander Reznicek | 2019-10-01 |
| 10410966 | BEOL embedded high density vertical resistor structure | Alexander Reznicek, Praneet Adusumilli | 2019-09-10 |
| 10411109 | Bipolar junction transistor (BJT) for liquid flow biosensing applications without a reference electrode and large sensing area | Alexander Reznicek, Tak H. Ning, Sufi Zafar | 2019-09-10 |
| 10396165 | Thin low defect relaxed silicon germanium layers on bulk silicon substrates | Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek | 2019-08-27 |
| 10388600 | Binary metallization structure for nanoscale dual damascene interconnects | Alexander Reznicek, Praneet Adusumilli, Koichi Motoyama | 2019-08-20 |
| 10388721 | Conformal capacitor structure formed by a single process | Praneet Adusumilli, Alexander Reznicek | 2019-08-20 |
| 10361277 | Low resistivity wrap-around contacts | Praneet Adusumilli, Adra Carr, Alexander Reznicek | 2019-07-23 |