Issued Patents All Time
Showing 76–100 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9361041 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura +2 more | 2016-06-07 |
| 9348523 | Code optimization to enable and disable coalescing of memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2016-05-24 |
| 9348620 | Using hardware transactional memory for implementation of queue operations | Jing Zheng | 2016-05-24 |
| 9348621 | Using hardware transactional memory for implementation of queue operations | Jing Zheng | 2016-05-24 |
| 9348643 | Prefetching of discontiguous storage locations as part of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2016-05-24 |
| 9342397 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Eric M. Schwarz | 2016-05-17 |
| 9336047 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2016-05-10 |
| 9336097 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2016-05-10 |
| 9329946 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2016-05-03 |
| 9329890 | Managing high-coherence-miss cache lines in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2016-05-03 |
| 9311178 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Eric M. Schwarz | 2016-04-12 |
| 9298626 | Managing high-conflict cache lines in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2016-03-29 |
| 9298623 | Identifying high-conflict cache lines in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2016-03-29 |
| 9292444 | Multi-granular cache management in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2016-03-22 |
| 9262206 | Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments | Harold W. Cain, III, Chung-Lung K. Shum, Timothy J. Slegel | 2016-02-16 |
| 9262343 | Transactional processing based upon run-time conditions | Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2016-02-16 |
| 9262207 | Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments | Harold W. Cain, III, Chung-Lung K. Shum, Timothy J. Slegel | 2016-02-16 |
| 9250980 | System, method, program, and code generation unit | Takuya Nakaike | 2016-02-02 |
| 9244782 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2016-01-26 |
| 9244781 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2016-01-26 |
| 9158573 | Dynamic predictor for coalescing memory transactions | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Eric M. Schwarz | 2015-10-13 |
| 9146774 | Coalescing memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2015-09-29 |
| 9135083 | Methods for single-owner multi-consumer work queues for repeatable tasks | Vijay A. Saraswat, Martin Vechev | 2015-09-15 |
| 9086974 | Centralized management of high-contention cache lines in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more | 2015-07-21 |
| 8972704 | Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory | Toshihiko Koju, Takuya Nakaike, Ali I. Sheikh, Harold W. Cain, III | 2015-03-03 |