MM

Maged M. Michael

IBM: 121 patents #407 of 70,183Top 1%
Globalfoundries: 3 patents #1,029 of 4,424Top 25%
📍 Danbury, CT: #5 of 826 inventorsTop 1%
🗺 Connecticut: #71 of 34,797 inventorsTop 1%
Overall (All Time): #9,327 of 4,157,543Top 1%
124
Patents All Time

Issued Patents All Time

Showing 26–50 of 124 patents

Patent #TitleCo-InventorsDate
9921834 Prefetching of discontiguous storage locations in anticipation of transactional execution Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more 2018-03-20
9921872 Interprocessor memory status communication Dan F. Greiner, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel 2018-03-20
9916180 Interprocessor memory status communication Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel 2018-03-13
9916179 Interprocessor memory status communication Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel 2018-03-13
9904581 System, method, program, and code generation unit Takuya Nakaike 2018-02-27
9904572 Dynamic prediction of hardware transaction resource requirements Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum 2018-02-27
9870253 Enabling end of transaction detection using speculative look ahead Michael K. Gschwind, Valentina Salapura 2018-01-16
9858074 Non-default instruction handling within transaction Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Valentina Salapura, Chung-Lung K. Shum 2018-01-02
9846593 Predicting the length of a transaction Jonathan D. Bradbury, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum +1 more 2017-12-19
9830185 Indicating nearing the completion of a transaction Jonathan D. Bradbury, Dan F. Greiner, Michael K. Gschwind, Chung-Lung K. Shum 2017-11-28
9824039 Signal interrupts in a transactional memory system Paul E. McKenney, Michael Wong 2017-11-21
9824040 Signal interrupts in a transactional memory system Paul E. McKenney, Michael Wong 2017-11-21
9772786 Address probing for transaction Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Eric M. Schwarz +2 more 2017-09-26
9766829 Address probing for transaction Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Eric M. Schwarz +2 more 2017-09-19
9766950 Methods for single-owner multi-consumer work queues for repeatable tasks Vijay A. Saraswat, Martin Vechev 2017-09-19
9760397 Interprocessor memory status communication Dan F. Greiner, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel 2017-09-12
9753764 Alerting hardware transactions that are about to run out of space Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura 2017-09-05
9740616 Multi-granular cache management in multi-processor computing environments Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more 2017-08-22
9720725 Prefetching of discontiguous storage locations as part of transactional execution Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz +1 more 2017-08-01
9720713 Using hardware transactional memory for implementation of queue operations Jing Zheng 2017-08-01
9696928 Memory transaction having implicit ordering effects Harold W. Cain, III, Kattamuri Ekanadham, Pratap C. Pattnaik, Derek E. Williams 2017-07-04
9696927 Memory transaction having implicit ordering effects Harold W. Cain, III, Kattamuri Ekanadham, Pratap C. Pattnaik, Derek E. Williams 2017-07-04
9690556 Code optimization to enable and disable coalescing of memory transactions Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum 2017-06-27
9645879 Salvaging hardware transactions with instructions Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz 2017-05-09
9639415 Salvaging hardware transactions with instructions Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz 2017-05-02