Issued Patents All Time
Showing 76–100 of 182 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9772867 | Control area for managing multiple threads in a computer | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2017-09-26 |
| 9760511 | Efficient interruption routing for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +7 more | 2017-09-12 |
| 9697135 | Suppressing virtual address translation utilizing bits and instruction tagging | Joerg Deutschle, Ute Gaertner | 2017-07-04 |
| 9678830 | Recovery improvement for quiesced systems | Michael Fee, Ute Gaertner, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski | 2017-06-13 |
| 9665424 | Recovery improvement for quiesced systems | Michael Fee, Ute Gaertner, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski | 2017-05-30 |
| 9652383 | Managing a collection of data | Jane H. Bartik, Damian L. Osisek, Donald W. Schmidt, Patrick M. West, Jr., Phil C. Yeh | 2017-05-16 |
| 9632780 | Diagnose instruction for serializing processing | — | 2017-04-25 |
| 9606799 | Performing a clear operation absent host intervention | Charles W. Gainey, Jr., Dan F. Greiner, Damian L. Osisek, Gustav E. Sittmann, III | 2017-03-28 |
| 9594661 | Method for executing a query instruction for idle time accumulation among cores in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2017-03-14 |
| 9594660 | Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2017-03-14 |
| 9594561 | Instruction stream tracing of multi-threaded processors | Lee Evan Eisen, Michael T. Huffer, Eric M. Schwarz | 2017-03-14 |
| 9542260 | Managing storage protection faults | Mark S. Farrell, Damian L. Osisek, Peter K. Szwed | 2017-01-10 |
| 9459875 | Dynamic enablement of multithreading | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +5 more | 2016-10-04 |
| 9454490 | Invalidating a range of two or more translation table entries and instruction therefore | Timothy J. Slegel, Erwin Pfeffer, Kenneth E. Plambeck | 2016-09-27 |
| 9454372 | Thread context restoration in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2016-09-27 |
| 9449314 | Virtualization of a central processing unit measurement facility | Patrick M. West, Jr., Phil C. Yeh | 2016-09-20 |
| 9417876 | Thread context restoration in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2016-08-16 |
| 9389897 | Exiting multiple threads of a simulation environment in a computer | Fadi Y. Busaba, Mark S. Farrell, Michael P. Mullen | 2016-07-12 |
| 9378128 | Dynamic address translation with fetch protection in an emulated environment | Dan F. Greiner, Charles W. Gainey, Jr., Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel +1 more | 2016-06-28 |
| 9372805 | Operating on translation look-aside buffers in a multiprocessor environment | Norbert Hagspiel, Ute Gaertner, Hanno Ulrich, Rebecca S. Wisniewski | 2016-06-21 |
| 9354873 | Performing a clear operation absent host intervention | Charles W. Gainey, Jr., Dan F. Greiner, Damian L. Osisek, Gustav E. Sittmann, III | 2016-05-31 |
| 9354883 | Dynamic enablement of multithreading | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +5 more | 2016-05-31 |
| 9330018 | Suppressing virtual address translation utilizing bits and instruction tagging | Joerg Deutschle, Ute Gaertner | 2016-05-03 |
| 9330017 | Suppressing virtual address translation utilizing bits and instruction tagging | Joerg Deutschle, Ute Gaertner | 2016-05-03 |
| 9323640 | Method and system for measuring the performance of a computer system on a per logical partition basis | Jane H. Bartik, Michael Billeci, Donald G. O'Brien, Bruce Wagar, Patrick M. West, Jr. | 2016-04-26 |