Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501304 | Glitch-less clock selector | David William Boerstler, Gary Dale Carpenter, Kevin John Nowka | 2002-12-31 |
| 6483888 | Clock divider with bypass and stop clock | David William Boerstler, Gary Dale Carpenter, Kevin John Nowka | 2002-11-19 |
| 6407574 | Method and system for utilizing hostile-switching neighbors to improve interconnect speed for high performance processors | Huajun Wen | 2002-06-18 |
| 6404235 | System and method for reducing latency in a dynamic circuit | Kevin John Nowka, Jieming Qi | 2002-06-11 |
| 6393446 | 32-bit and 64-bit dual mode rotator | Sang Hoo Dhong, Jaehong Park, Joel A. Silberman | 2002-05-21 |
| 6360238 | Leading zero/one anticipator having an integrated sign selector | Sang Hoo Dhong, Kyung Tek Lee, Kevin John Nowka | 2002-03-19 |
| 6345286 | 6-to-3 carry-save adder | Sang Hoo Dhong, Kevin John Nowka | 2002-02-05 |
| 6335900 | Method and apparatus for selectable wordline boosting in a memory device | Ohsang Kwon, Kevin John Nowka | 2002-01-01 |
| 6335650 | Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages | David William Boerstler, Harm Peter Hofstee, Kevin John Nowka | 2002-01-01 |
| 6292027 | Fast low-power logic gates and method for evaluating logic signals | Sand Hoo Dhong, Jaehong Park, Osamu Takahashi | 2001-09-18 |
| 6285218 | Method and apparatus for implementing logic using mask-programmable dynamic logic gates | Sang Hoo Dhong, Jaehong Park, Osamu Takahashi | 2001-09-04 |
| 6282557 | Low latency fused multiply-adder | Sang Hoo Dhong, Kevin John Nowka | 2001-08-28 |
| 6232872 | Comparator | Sang Hoo Dhong, Jaehong Park | 2001-05-15 |
| 6178437 | Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor | Sang Hoo Dhong, Kevin John Nowka | 2001-01-23 |
| 6175852 | High-speed binary adder | Sang Hoo Dhong, Kevin John Nowka | 2001-01-16 |
| 5964827 | High-speed binary adder | Sang Hoo Dhong, Joel A. Silberman | 1999-10-12 |
| 5881274 | Method and apparatus for performing add and rotate as a single instruction within a processor | Joel A. Silberman, Sang Hoo Dhong | 1999-03-09 |
| 5757682 | Parallel calculation of exponent and sticky bit during normalization | Eric M. Schwarz, Robert M. Bunce, Leon Sigal | 1998-05-26 |
| 5742535 | Parallel calculation of exponent and sticky bit during normalization | Eric M. Schwarz, Robert M. Bunce, Leon Sigal | 1998-04-21 |
| 5742536 | Parallel calculation of exponent and sticky bit during normalization | Eric M. Schwarz, Robert M. Bunce, Leon Sigal | 1998-04-21 |
| 5627774 | Parallel calculation of exponent and sticky bit during normalization | Eric M. Schwarz, Robert M. Bunce, Leon Sigal | 1997-05-06 |
| 5375223 | Single register arbiter circuit | Steven D. Meyers, Paul Richard Schwartz | 1994-12-20 |