Issued Patents All Time
Showing 26–50 of 472 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11157408 | Cache snooping mode extending coherence protection for certain requests | Derek E. Williams, Hugh Shen, Luke Murray | 2021-10-26 |
| 11119781 | Synchronized access to data in shared memory by protecting the load target address of a fronting load | Derek E. Williams, Hugh Shen, Sanjeev Ghai | 2021-09-14 |
| 11106608 | Synchronizing access to shared memory by extending protection for a target address of a store-conditional request | Derek E. Williams, Hugh Shen, Sanjeev Ghai | 2021-08-31 |
| 11086672 | Low latency management of processor core wait state | Derek E. Williams, Hugh Shen | 2021-08-10 |
| 11074205 | Managing efficient selection of a particular processor thread for handling an interrupt | Richard Louis Arndt, Florian A. Auernhammer, Wayne M. Barrett, Robert Allen Drehmel, Michael S. Siegel +1 more | 2021-07-27 |
| 11068407 | Synchronized access to data in shared memory by protecting the load target address of a load-reserve instruction | Derek E. Williams | 2021-07-20 |
| 10997075 | Adaptively enabling and disabling snooping bus commands | Hien Minh Le, Hugh Shen, Derek E. Williams, Phillip G. Williams | 2021-05-04 |
| 10977183 | Processing a sequence of translation entry invalidation requests with regard to draining a processor core | Derek E. Williams, Hugh Shen | 2021-04-13 |
| 10977035 | Atomic memory operation having selectable location of performance | Derek E. Williams | 2021-04-13 |
| 10970215 | Cache snooping mode extending coherence protection for certain requests | Derek E. Williams, Hugh Shen, Luke Murray | 2021-04-06 |
| 10956070 | Zeroing a memory block without processor caching | Derek E. Williams, Hugh Shen | 2021-03-23 |
| 10949346 | Data flush of a persistent memory cache or buffer | Derek E. Williams, John Steven Dodson | 2021-03-16 |
| 10884740 | Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads | Derek E. Williams, Kimberly M. Fernsler, Hugh Shen | 2021-01-05 |
| 10831607 | Dynamic transaction throttling in a data processing system supporting transactional memory | Derek E. Williams, Hugh Shen, Sanjeev Ghai, Hung Q. Doan | 2020-11-10 |
| 10831660 | Ordering execution of an interrupt handler | Derek E. Williams, Hugh Shen | 2020-11-10 |
| 10824567 | Selectively preventing pre-coherence point reads in a cache hierarchy to reduce barrier overhead | Derek E. Williams, Hugh Shen, William J. Starke | 2020-11-03 |
| 10740239 | Translation entry invalidation in a multithreaded data processing system | Derek E. Williams, Hugh Shen | 2020-08-11 |
| 10733102 | Selectively updating a coherence state in response to a storage update | Derek E. Williams | 2020-08-04 |
| 10725937 | Synchronized access to shared memory by extending protection for a store target address of a store-conditional request | Derek E. Williams, Hugh Shen, Sanjeev Ghai | 2020-07-28 |
| 10705957 | Selectively updating a coherence state in response to a storage update | Derek E. Williams | 2020-07-07 |
| 10691599 | Selectively updating a coherence state in response to a storage update | Derek E. Williams | 2020-06-23 |
| 10691605 | Expedited servicing of store operations in a data processing system | Hugh Shen, Jeffrey A. Stuecheli, Derek E. Williams | 2020-06-23 |
| 10671537 | Reducing translation latency within a memory management unit using external caching structures | Jody B. Joyner, Ronald Nick Kalla, Michael S. Siegel, Jeffrey A. Stuecheli, Charles D. Wait +1 more | 2020-06-02 |
| 10649902 | Reducing translation latency within a memory management unit using external caching structures | Jody B. Joyner, Ronald Nick Kalla, Michael S. Siegel, Jeffrey A. Stuecheli, Charles D. Wait +1 more | 2020-05-12 |
| 10649901 | Victim cache line selection | Bernard C. Drerup, Jeffrey A. Stuecheli, Phillip G. Williams | 2020-05-12 |