Issued Patents All Time
Showing 351–375 of 472 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6785774 | High performance symmetric multiprocessing systems via super-coherent data mechanisms | Ravi Kumar Arimilli, William J. Starke, Derek E. Williams | 2004-08-31 |
| 6779086 | Symmetric multiprocessor systems with an independent super-coherent cache directory | Ravi Kumar Arimilli, William J. Starke, Derek E. Williams | 2004-08-17 |
| 6763433 | High performance cache intervention mechanism for symmetric multiprocessor systems | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2004-07-13 |
| 6763435 | Super-coherent multiprocessor system bus protocols | Ravi Kumar Arimilli, William J. Starke, Derek E. Williams | 2004-07-13 |
| 6763434 | Data processing system and method for resolving a conflict between requests to modify a shared cache line | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2004-07-13 |
| 6748518 | Multi-level multiprocessor speculation mechanism | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2004-06-08 |
| 6748501 | Microprocessor reservation mechanism for a hashed address system | Ravi Kumar Arimilli, Robert Alan Cargnoni, Derek E. Williams | 2004-06-08 |
| 6728873 | System and method for providing multiprocessor speculation within a speculative branch path | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2004-04-27 |
| 6725340 | Mechanism for folding storage barrier operations in a multiprocessor system | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2004-04-20 |
| 6721856 | Enhanced cache management mechanism via an intelligent system bus monitor | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2004-04-13 |
| 6721853 | High performance data processing system via cache victimization protocols | Ravi Kumar Arimilli, James Stephen Fields, Jr., John Steven Dodson | 2004-04-13 |
| 6704844 | Dynamic hardware and software performance optimizations for super-coherent SMP systems | Ravi Kumar Arimilli, William J. Starke, Derek E. Williams | 2004-03-09 |
| 6704843 | Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2004-03-09 |
| 6691220 | Multiprocessor speculation mechanism via a barrier speculation flag | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2004-02-10 |
| 6671712 | Multi-node data processing system having a non-hierarchical interconnect architecture | Ravi Kumar Arimilli, James Stephen Fields, Jr., Jody B. Joyner, Jerry Don Lewis | 2003-12-30 |
| 6662275 | Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache | Ravi Kumar Arimilli, John Steven Dodson | 2003-12-09 |
| 6658556 | Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Jerry Don Lewis | 2003-12-02 |
| 6658539 | Super-coherent data mechanisms for shared caches in a multiprocessing system | Ravi Kumar Arimilli, William J. Starke, Derek E. Williams | 2003-12-02 |
| 6631450 | Symmetric multiprocessor address bus protocol with intra-cache line access information | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2003-10-07 |
| 6629214 | Extended cache coherency protocol with a persistent “lock acquired” state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-09-30 |
| 6629209 | Cache coherency protocol permitting sharing of a locked data granule | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-09-30 |
| 6629210 | Intelligent cache management mechanism via processor access sequence analysis | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr. | 2003-09-30 |
| 6629212 | High speed lock acquisition mechanism with time parameterized cache coherency states | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-09-30 |
| 6625660 | Multiprocessor speculation mechanism for efficiently managing multiple barrier operations | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2003-09-23 |
| 6625701 | Extended cache coherency protocol with a modified store instruction lock release indicator | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke | 2003-09-23 |