Issued Patents All Time
Showing 301–325 of 472 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7401189 | Pipelining D states for MRU steerage during MRU/LRU member allocation | Robert H. Bell, Jr., William J. Starke, Jeffrey A. Stuecheli | 2008-07-15 |
| 7386682 | Reducing number of rejected snoop requests by extending time to respond to snoop request | Hugh Shen, William J. Starke, Derek E. Williams | 2008-06-10 |
| 7386678 | Efficient system bootstrap loading | Jeffrey William Kellington, Kevin F. Reick, Hugh Shen | 2008-06-10 |
| 7386681 | Reducing number of rejected snoop requests by extending time to respond to snoop request | Hugh Shen, William J. Starke, Derek E. Williams | 2008-06-10 |
| 7366841 | L2 cache array topology for large cache with different latency domains | Leo James Clark, Kirk Samuel Livingston, William J. Starke | 2008-04-29 |
| 7366844 | Data processing system and method for handling castout collisions | Sanjeev Ghai, John T. Hollaway, Jr. | 2008-04-29 |
| 7363433 | Cache member protection with partial make MRU allocation | Robert H. Bell, Jr., William J. Starke, Jeffrey A. Stuecheli | 2008-04-22 |
| 7360021 | System and method for completing updates to entire cache lines with address-only bus operations | Ravi Kumar Arimilli, Hugh Shen, Derek E. Williams | 2008-04-15 |
| 7360041 | Method for priority scheduling and priority dispatching of store conditional operations in a store queue | Hugh Shen, Derek E. Williams | 2008-04-15 |
| 7343455 | Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation | Robert H. Bell, Jr., William J. Starke | 2008-03-11 |
| 7340568 | Reducing number of rejected snoop requests by extending time to respond to snoop request | Benjiman L. Goodman, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams | 2008-03-04 |
| 7337280 | Data processing system and method for efficient L3 cache directory management | William J. Starke, Derek E. Williams, Philip G. Williams | 2008-02-26 |
| 7308537 | Half-good mode for large L2 cache array topology with different latency domains | James Stephen Fields, Jr., Kirk Samuel Livingston, William J. Starke | 2007-12-11 |
| 7308536 | System bus read data transfers with data ordering control bits | Ravi Kumar Arimilli, Vicente Enrique Chung, Jody B. Joyner | 2007-12-11 |
| 7305523 | Cache memory direct intervention | William J. Starke, Derek E. Williams | 2007-12-04 |
| 7305522 | Victim cache using direct intervention | Leo James Clark, James Stephen Fields, Jr., Bradley McCredie, William J. Starke | 2007-12-04 |
| 7284102 | System and method of re-ordering store operations within a processor | Hugh Shen, William J. Starke, Derek E. Williams | 2007-10-16 |
| 7284097 | Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes | John Steven Dodson, James Stephen Fields, Jr., Kenneth L. Wright | 2007-10-16 |
| 7272773 | Cache directory array recovery mechanism to support special ECC stuck bit matrix | Robert Alan Cargnoni, Kirk Samuel Livingston, William J. Starke | 2007-09-18 |
| 7272664 | Cross partition sharing of state information | Ravi Kumar Arimilli, Robert Alan Cargnoni, William J. Starke | 2007-09-18 |
| 7254694 | Processors interconnect fabric with relay broadcasting and accumulation of partial responses | Leo James Clark, James Stephen Fields, Jr., William J. Starke, Jeffrey A. Stuecheli | 2007-08-07 |
| 7237070 | Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source | Aaron C. Sawdey, William J. Starke, Derek E. Williams | 2007-06-26 |
| 7228385 | Processor, data processing system and method for synchronizing access to data in shared memory | Sheldon B. Levenstein, William J. Starke, Derek E. Williams | 2007-06-05 |
| 7200717 | Processor, data processing system and method for synchronizing access to data in shared memory | Sheldon B. Levenstein, William J. Starke, Derek E. Williams | 2007-04-03 |
| 7197604 | Processor, data processing system and method for synchronzing access to data in shared memory | Sheldon B. Levenstein, William J. Starke, Derek E. Williams | 2007-03-27 |