Issued Patents All Time
Showing 326–350 of 472 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7117319 | Managing processor architected state upon an interrupt | Ravi Kumar Arimilli, Robert Alan Cargnoni, William J. Starke | 2006-10-03 |
| 7103721 | Cache allocation mechanism for biasing subsequent allocations based upon cache directory state | Robert Alan Cargnoni, William J. Starke, Jeffrey A. Stuecheli | 2006-09-05 |
| 7073043 | Multiprocessor system supporting multiple outstanding TLBI operations per partition | Ravi Kumar Arimilli, Kirk Samuel Livingston | 2006-07-04 |
| 7069494 | Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism | Robert Alan Cargnoni, Kirk Samuel Livingston, William J. Starke | 2006-06-27 |
| 7055002 | Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability | Robert Alan Cargnoni, Kevin F. Reick, Derek E. Williams | 2006-05-30 |
| 7055003 | Data cache scrub mechanism for large L2/L3 data cache structures | Robert Alan Cargnoni, Harmony L. Helterhoff, Kevin F. Reick | 2006-05-30 |
| 7047320 | Data processing system providing hardware acceleration of input/output (I/O) communication | Ravi Kumar Arimilli, Robert Alan Cargnoni, William J. Starke | 2006-05-16 |
| 7039832 | Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems | Ravi Kumar Arimilli, Robert Alan Cargnoni, William J. Starke | 2006-05-02 |
| 6996679 | Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members | Robert Alan Cargnoni, William J. Starke | 2006-02-07 |
| 6983347 | Dynamically managing saved processor soft states | Ravi Kumar Arimilli, Robert Alan Cargnoni, William J. Starke | 2006-01-03 |
| 6981083 | Processor virtualization mechanism via an enhanced restoration of hard architected states | Ravi Kumar Arimilli, Robert Alan Cargnoni, William J. Starke | 2005-12-27 |
| 6976148 | Acceleration of input/output (I/O) communication through improved address translation | Ravi Kumar Arimilli, Robert Alan Cargnoni, William J. Starke | 2005-12-13 |
| 6970976 | Layered local cache with lower level cache optimizing allocation mechanism | Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson | 2005-11-29 |
| 6963967 | System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2005-11-08 |
| 6950909 | System and method for reducing contention in a multi-sectored cache | Derek E. Williams | 2005-09-27 |
| 6944721 | Asynchronous non-blocking snoop invalidation | Ravi Kumar Arimilli | 2005-09-13 |
| 6910062 | Method and apparatus for transmitting packets within a symmetric multiprocessor system | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2005-06-21 |
| 6880073 | Speculative execution of instructions and processes before completion of preceding barrier operations | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2005-04-12 |
| 6874063 | System bus read data transfers with data ordering control bits | Ravi Kumar Arimilli, Vicente Enrique Chung, Jody B. Joyner | 2005-03-29 |
| 6848003 | Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response | Ravi Kumar Arimilli, James Stephen Fields, Jr., Jody B. Joyner, Jerry Don Lewis | 2005-01-25 |
| 6826655 | Apparatus for imprecisely tracking cache line inclusivity of a higher level cache | Ravi Kumar Arimilli | 2004-11-30 |
| 6826654 | Cache invalidation bus for a highly scalable shared cache memory hierarchy | Ravi Kumar Arimilli | 2004-11-30 |
| 6823471 | Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Jerry Don Lewis | 2004-11-23 |
| 6813694 | Local invalidation buses for a highly scalable shared cache memory hierarchy | Ravi Kumar Arimilli | 2004-11-02 |
| 6801984 | Imprecise snooping based invalidation mechanism | Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis | 2004-10-05 |