Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9515252 | Low degradation MRAM encapsulation process using silicon-rich silicon nitride film | Anthony J. Annunziata, Chandrasekaran Kothandaraman, Junghyuk Lee, Nathan P. Marchack, Deborah A. Neumayer +2 more | 2016-12-06 |
| 9502640 | Structure and method to reduce shorting in STT-MRAM device | Anthony J. Annunziata, Nathan P. Marchack | 2016-11-22 |
| 9496184 | III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2016-11-15 |
| 9466673 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Isaac Lauer, Alexander Reznicek, Jeffrey W. Sleight | 2016-10-11 |
| 9450180 | Structure and method to reduce shorting in STT-MRAM device | Anthony J. Annunziata, Nathan P. Marchack | 2016-09-20 |
| 9397287 | Magnetic tunnel junction with post-deposition hydrogenation | Anthony J. Annunziata, Chandrasekharan Kothandaraman | 2016-07-19 |
| 9391163 | Stacked planar double-gate lamellar field-effect transistor | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2016-07-12 |
| 9373638 | Complementary metal-oxide silicon having silicon and silicon germanium channels | Isaac Lauer, Alexander Reznicek, Jeffrey W. Sleight | 2016-06-21 |
| 9240324 | Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor | Matthew J. BrightSky, Chung H. Lam | 2016-01-19 |
| 9209086 | Low temperature salicide for replacement gate nanowires | Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2015-12-08 |
| 9209095 | III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2015-12-08 |
| 9105650 | Lateral bipolar transistor and CMOS hybrid technology | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2015-08-11 |
| 9012970 | Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor | Matthew J. BrightSky, Chung H. Lam | 2015-04-21 |
| 8927431 | High-rate chemical vapor etch of silicon substrates | Stephen W. Bedell, Isaac Lauer, Joseph S. Newbury | 2015-01-06 |
| 8853662 | Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor | Matthew J. BrightSky, Chung H. Lam | 2014-10-07 |
| 8835898 | Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor | Matthew J. BrightSky, Chung H. Lam | 2014-09-16 |
| 8673717 | Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor | Matthew J. BrightSky, Chung H. Lam | 2014-03-18 |
| 8617957 | Fin bipolar transistors having self-aligned collector and emitter regions | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2013-12-31 |
| 8618636 | Fin bipolar transistors having self-aligned collector and emitter regions | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2013-12-31 |
| 8614117 | Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor | Matthew J. BrightSky, Chung H. Lam | 2013-12-24 |
| 8610181 | V-groove source/drain MOSFET and process for fabricating same | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2013-12-17 |
| 8603868 | V-groove source/drain MOSFET and process for fabricating same | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2013-12-10 |
| 8592250 | Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor | Matthew J. BrightSky, Chung H. Lam | 2013-11-26 |