Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8914272 | Visualizing sensitivity information in integrated circuit design | Sani R. Nassif | 2014-12-16 |
| 8595664 | Guiding design actions for complex failure modes | Sani R. Nassif | 2013-11-26 |
| 7991574 | Techniques for filtering systematic differences from wafer evaluation parameters | — | 2011-08-02 |
| 7759960 | Integrated circuit testing methods using well bias modification | David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn +1 more | 2010-07-20 |
| 7564256 | Integrated circuit testing methods using well bias modification | David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn +1 more | 2009-07-21 |
| 7486098 | Integrated circuit testing method using well bias modification | David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn +1 more | 2009-02-03 |
| 7428675 | Testing using independently controllable voltage islands | Phil Nigh, Leah Pastel, Steven F. Oakland, Jody VanHorn, Paul S. Zuchowski | 2008-09-23 |
| 7400162 | Integrated circuit testing methods using well bias modification | David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn +1 more | 2008-07-15 |
| 7127690 | Method and system for defect evaluation using quiescent power plane current (IDDQ) voltage linearity | Phillip J. Nigh | 2006-10-24 |
| 6941235 | Method and system for analyzing quiescent power plane current (IDDQ) test data in very-large scale integrated (VLSI) circuits | — | 2005-09-06 |
| 6618682 | Method for test optimization using historical and actual fabrication test data | Raymond J. Bulaga, John L. Harris, Phillip J. Nigh, Leo A. Noel, William J. Thibault +2 more | 2003-09-09 |
| 6175244 | Current signatures for IDDQ testing | Wojciech P. Maly | 2001-01-16 |