Issued Patents All Time
Showing 26–50 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9324030 | System interconnect dynamic scaling by predicting I/O requirements | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman, David J. Krolak | 2016-04-26 |
| 9324031 | System interconnect dynamic scaling by predicting I/O requirements | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman, David J. Krolak | 2016-04-26 |
| 9252131 | Chip stack cache extension with coherency | Edgar R. Cordero, Subrat K. Panda, Saravanan Sethuraman, Diyanesh Babu C. Vidyapoornachary | 2016-02-02 |
| 9244799 | Bus interface optimization by selecting bit-lanes having best performance margins | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2016-01-26 |
| 9217771 | Method for breaking down hardware power into sub-components | Nagashyamala R. Dhanwada, Arun Joseph, Charles R. Lefurgy, Diwesh Pandey | 2015-12-22 |
| 9087135 | Characterization and validation of processor links | Robert W. Berry, Jr., Prasanna Jayaraman | 2015-07-21 |
| 9052840 | Accessing additional memory space with multiple processors | Edgar R. Cordero, Diyanesh Babu C. Vidyapoornachary, Robert B. Tremaine | 2015-06-09 |
| 9047057 | Accessing additional memory space with multiple processors | Edgar R. Cordero, Diyanesh Babu C. Vidyapoornachary, Robert B. Tremaine | 2015-06-02 |
| 9021411 | Characterizing TSV structures in a semiconductor chip stack | Subramanian S. Iyer, Saravanan Sethuraman, Ming Yin | 2015-04-28 |
| 9020779 | Detecting cross-talk on processor links | Robert W. Berry, Jr., Prasanna Jayaraman | 2015-04-28 |
| 8984335 | Core diagnostics and repair | Sreekala Anandavally, Gerard M. Salem, Diyanesh B.C. Vidyapoornachary | 2015-03-17 |
| 8977895 | Multi-core diagnostics and repair using firmware and spare cores | Sreekala Anandavally, Gerard M. Salem, Diyanesh B.C. Vidyapoornachary | 2015-03-10 |
| 8962475 | Multi-layer circuit substrate fabrication method providing improved transmission line integrity and increased routing density | Sungjun Chun, Roger D. Weekly | 2015-02-24 |
| 8832513 | Characterization and validation of processor links | Robert W. Berry, Jr., Prasanna Jayaraman | 2014-09-09 |
| 8826092 | Characterization and validation of processor links | Robert W. Berry, Jr., Prasanna Jayaraman | 2014-09-02 |
| 8813000 | System for designing substrates having reference plane voids with strip segments | Sungjun Chun, Roger D. Weekly | 2014-08-19 |
| 8645889 | Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules | Jinwoo Choi, Sungjun Chun, Roger D. Weekly | 2014-02-04 |
| 8638567 | Circuit manufacturing and design techniques for reference plane voids with strip segment | Sungjun Chun, Roger D. Weekly | 2014-01-28 |
| 8625300 | Circuit manufacturing and design techniques for reference plane voids with strip segment | Sungjun Chun, Roger D. Weekly | 2014-01-07 |
| 8624297 | Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density | Sungjun Chun, Roger D. Weekly | 2014-01-07 |
| 8407644 | Reducing crosstalk in the design of module nets | Dulce M. Altabella Cabrera, Sungjun Chun, Tingdong Zhou | 2013-03-26 |
| 8325490 | Circuit manufacturing and design techniques for reference plane voids with strip segment | Sungjun Chun, Roger D. Weekly | 2012-12-04 |
| 8295058 | Structure for enhancing reference return current conduction | Joseph J. Cahill, Roger D. Weekly | 2012-10-23 |
| 8288657 | Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules | Jinwoo Choi, Sungjun Chun, Roger D. Weekly | 2012-10-16 |
| 8055486 | Power delivery analysis and design | Daniel Douriet, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly | 2011-11-08 |