Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6747563 | Removable memory cartridge system for use with a server or other processor-based device | Christian Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren +6 more | 2004-06-08 |
| 6715116 | Memory data verify operation | Robert A. Lester, John M. MacLaren, Patrick L. Ferguson | 2004-03-30 |
| 6692293 | Technique for identifying multiple circuit components | John M. MacLaren | 2004-02-17 |
| 6684292 | Memory module resync | Gary J. Piccirillo, Jerome J. Johnson | 2004-01-27 |
| 6640282 | Hot replace power control sequence logic | John M. MacLaren, Jerome J. Johnson, Robert A. Lester, Gary J. Piccirillo, Christian Post +3 more | 2003-10-28 |
| 6608564 | Removable memory cartridge system for use with a server or other processor-based device | Christian Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John M. MacLaren +6 more | 2003-08-19 |
| 6517375 | Technique for identifying multiple circuit components | John M. MacLaren | 2003-02-11 |
| 6275885 | System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache | Kenneth T. Chin, Michael J. Collins, Robert A. Lester | 2001-08-14 |
| 6247102 | Computer system employing memory controller and bridge interface permitting concurrent operation | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo +3 more | 2001-06-12 |
| 6209067 | Computer system controller and method with processor write posting hold off on PCI master memory request | Michael J. Collins, Michael Moriarty, Jens K. Ramsey | 2001-03-27 |
| 5974501 | Method and apparatus for detecting memory device types | Charles N. Shaver, Timothy R. Zinsky, Paul J. Broyles | 1999-10-26 |
| 5960459 | Memory controller having precharge prediction based on processor and PCI bus cycles | Gary W. Thome, Michael Moriarty | 1999-09-28 |
| 5938739 | Memory controller including write posting queues, bus read control logic, and a data contents counter | Michael J. Collins, Gary W. Thome, Michael Moriarty, Jens K. Ramsey | 1999-08-17 |
| 5819105 | System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device | Michael Moriarty, Michael J. Collins, Gary W. Thome | 1998-10-06 |
| 5813038 | Memory controller having precharge prediction based on processor and PC bus cycles | Gary W. Thome, Michael Moriarty | 1998-09-22 |
| 5781925 | Method of preventing cache corruption during microprocessor pipelined burst operations | Jens K. Ramsey, Jeffrey C. Stevens, Michael J. Collins | 1998-07-14 |
| 5778413 | Programmable memory controller having two level look-up for memory timing parameter | Jeffrey C. Stevens, Gary W. Thome, Michael J. Collins, Michael Moriarty | 1998-07-07 |
| 5721935 | Apparatus and method for entering low power mode in a computer system | Todd Deschepper, James R. Reif, James R. Edwards, Michael J. Collins | 1998-02-24 |
| 5701433 | Computer system having a memory controller which performs readahead operations which can be aborted prior to completion | Michael Moriarty | 1997-12-23 |
| 5634073 | System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation | Michael J. Collins, Gary W. Thome, Michael Moriarty, Jens K. Ramsey | 1997-05-27 |
| 5634112 | Memory controller having precharge prediction based on processor and PCI bus cycles | Gary W. Thome, Michael Moriarty | 1997-05-27 |
| 5524235 | System for arbitrating access to memory with dynamic priority assignment | Michael Moriarty, Michael J. Collins, Gary W. Thome | 1996-06-04 |
| 4930106 | Dual cache RAM for rapid invalidation | Michael Danilenko, Clarence W. DeKarske | 1990-05-29 |