Issued Patents All Time
Showing 101–125 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5528062 | High-density DRAM structure on soi | Chang-Ming Hsieh, Louis L. Hsu | 1996-06-18 |
| 5516726 | Method of manufacturing local interconnection for semiconductors | Paul Kim | 1996-05-14 |
| 5516721 | Isolation structure using liquid phase oxide deposition | Carol Galli, Louis L. Hsu, Joseph F. Shepard, Jr. | 1996-05-14 |
| 5466625 | Method of making a high-density DRAM structure on SOI | Chang-Ming Hsieh, Louis L. Hsu | 1995-11-14 |
| 5389559 | Method of forming integrated interconnect for very high density DRAMs | Chang-Ming Hsieh, Louis L. Hsu, Toshio Mii, Joseph F. Shepard, Jr. | 1995-02-14 |
| 5384277 | Method for forming a DRAM trench cell capacitor having a strap connection | Louis L. Hsu, Toshio Mii, Joseph F. Shepard, Jr. | 1995-01-24 |
| 5376578 | Method of fabricating a semiconductor device with raised diffusions and isolation | Louis L. Hsu, Joseph F. Shepard, Jr. | 1994-12-27 |
| 5369049 | DRAM cell having raised source, drain and isolation | Joyce Elizabeth Acocella, Louis L. Hsu, Nivo Rovedo, Joseph F. Shepard, Jr. | 1994-11-29 |
| 5340759 | Method of making a vertical gate transistor with low temperature epitaxial channel | Chang-Ming Hsieh, Louis L. Hsu | 1994-08-23 |
| 5334281 | Method of forming thin silicon mesas having uniform thickness | George Doerre, Nivo Rovedo | 1994-08-02 |
| 5283456 | Vertical gate transistor with low temperature epitaxial channel | Chang-Ming Hsieh, Louis L. Hsu | 1994-02-01 |
| 5258318 | Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon | Taqi Nasser Buti, Louis L. Hsu, Mark E. Jost, Ronald N. Schulz | 1993-11-02 |
| 5241203 | Inverse T-gate FET transistor with lightly doped source and drain region | Louis L. Hsu, Joseph F. Shepard, Jr., Paul J. Tsang | 1993-08-31 |
| 5155572 | Vertical isolated-collector PNP transistor structure | Dominique Bonneau, Myriam Combes, Anthony J. Dally, Pierre Mollier, Pascal Tannhof | 1992-10-13 |
| 5120668 | Method of forming an inverse T-gate FET transistor | Louis L. Hsu, Joseph F. Shepard, Jr., Paul J. Tsang | 1992-06-09 |
| H986 | Field effect-transistor with asymmetrical structure | Christopher F. Codella, Nivo Rovedo | 1991-11-05 |
| 5023478 | Complementary emitter follower drivers | Gerard Boudon, Pierre Mollier, Dominique Omet, Pascal Tannhof, Franck Wallart | 1991-06-11 |
| 4982257 | Vertical bipolar transistor with collector and base extensions | Shah Akbar, Patricia L. Kroesen, Nivo Rovedo | 1991-01-01 |
| 4957875 | Vertical bipolar transistor | Shah Akbar, Patricia L. Kroesen, Nivo Rovedo | 1990-09-18 |
| 4868135 | Method for manufacturing a Bi-CMOS device | Nivo Rovedo | 1989-09-19 |
| 4855246 | Fabrication of a GaAs short channel lightly doped drain MESFET | Christopher F. Codella | 1989-08-08 |
| 4729006 | Sidewall spacers for CMOS circuit stress relief/isolation and method for making | Anthony J. Dally, Jacob Riseman, Nivo Rovedo | 1988-03-01 |
| 4689113 | Process for forming planar chip-level wiring | Karanam Balasubramanyam, Anthony J. Dally, Jacob Riseman | 1987-08-25 |
| 4671851 | Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique | Klaus D. Beyer, James S. Makris, Eric Mendel, Karen A. Nummy, Jacob Riseman +1 more | 1987-06-09 |
| 4648937 | Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer | Jacob Riseman, Nivo Rovedo, Ronald N. Schulz | 1987-03-10 |