Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6446189 | Computer system including a novel address translation mechanism | Gerald D. Zuraski, Jr., William A. Hughes, William Kurt Lewchuk, Scott White, Michael T. Clark | 2002-09-03 |
| 6425074 | Method and apparatus for rapid execution of FCOM and FSTSW | Stephan G. Meier, Norbert Juffa, Stuart F. Oberman | 2002-07-23 |
| 6397238 | Method and apparatus for rounding in a multiplier | Stuart F. Oberman, Norbert Juffa, Ming Siu, Ravikrishna Cherukuri | 2002-05-28 |
| 6393555 | Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit | Stephan G. Meier, Norbert Juffa, Stuart F. Oberman | 2002-05-21 |
| 6381625 | Method and apparatus for calculating a power of an operand | Stuart F. Oberman, Norbert Juffa, Ming Siu, Ravikrishna Cherukuri | 2002-04-30 |
| 6370637 | Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria | Stephan G. Meier, Norbert Juffa, Stuart F. Oberman | 2002-04-09 |
| 6330649 | Multiprocessor digital data processing system | Steven J. Frank, Henry Burkhardt, III, Linda O. Lee, Nathan Goodman, Benson Margulies | 2001-12-11 |
| 6298438 | System and method for conditional moving an operand from a source register to destination register | John S. Thayer, John G. Favor | 2001-10-02 |
| 6266803 | Method for placement of clock buffers in a clock distribution system | Alisa M. Scherer | 2001-07-24 |
| 6223198 | Method and apparatus for multi-function arithmetic | Stuart F. Oberman, Norbert Juffa, Ming Siu, Ravikrishna Cherukuri | 2001-04-24 |
| 6173366 | Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage | John S. Thayer, John G. Favor | 2001-01-09 |
| 6154831 | Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values | John S. Thayer, Gary W. Thome, John G. Favor | 2000-11-28 |
| 6141673 | Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions | John S. Thayer, John G. Favor | 2000-10-31 |
| 6105129 | Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction | Stephan G. Meier, Norbert Juffa, Michael Achenbach | 2000-08-15 |
| 6093213 | Flexible implementation of a system management mode (SMM) in a processor | John G. Favor | 2000-07-25 |
| 6087872 | Dynamic latch circuitry | Hamid Partovi, Robert C. Burd, Udin Salim, Luigi Di Gregorio, Donald A. Draper | 2000-07-11 |
| 6061521 | Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle | John S. Thayer, Gary W. Thome, John G. Favor | 2000-05-09 |
| 6047372 | Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot | John S. Thayer, Brian E. Longhenry, John G. Favor | 2000-04-04 |
| 6009505 | System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot | John S. Thayer, Gary W. Thome, Brian E. Longhenry, John G. Favor | 1999-12-28 |
| 5990717 | Latching method | Hamid Partovi, Robert C. Burd, Udin Salim, Luigi Di Gregorio, Donald A. Draper | 1999-11-23 |
| 5960461 | Multiprocessor digital data processing system/shared memory multiprocessor system and method of operation | Steven J. Frank, Henry Burkhardt, III, Linda O. Lee, Nathan Goodman, Benson Margulies | 1999-09-28 |
| 5909572 | System and method for conditionally moving an operand from a source register to a destination register | John S. Thayer, John G. Favor | 1999-06-01 |
| 5822578 | System for inserting instructions into processor instruction stream in order to perform interrupt processing | Steven J. Frank, Henry Burkhardt, III, Linda Q. Lee, John A. Roskosz, Brett D. Byers +2 more | 1998-10-13 |
| 5801975 | Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles | John S. Thayer, John G. Favor | 1998-09-01 |
| 5790841 | Method for placement of clock buffers in a clock distribution system | Alisa M. Scherer | 1998-08-04 |