Issued Patents All Time
Showing 51–60 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8841732 | Self-adjusting latch-up resistance for CMOS devices | Xiaodong Yang, Gan Wang | 2014-09-23 |
| 8835292 | Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer | Michael P. Chudzik, Min Dai, Xiang Hu, Jinping Liu, Xiaodong Yang | 2014-09-16 |
| 8809178 | Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents | Michael Hargrove, Xiaodong Yang, Hans Van Meer, Laegu Kang, Christian Gruensfelder +1 more | 2014-08-19 |
| 8809962 | Transistor with reduced parasitic capacitance | Jinping Liu, Min Dai, Xiaodong Yang | 2014-08-19 |
| 8691646 | FINFET compatible PC-bounded ESD diode | Jerome Ciavatti | 2014-04-08 |
| 8669616 | Method for forming N-shaped bottom stress liner | Xiaodong Yang, Vara Govindeswara Reddy Vakada, Jinping Liu, Min Dai | 2014-03-11 |
| 8664717 | Semiconductor device with an oversized local contact as a Faraday shield | Young Way Teh, Vara Govindeswara Reddy Vakada | 2014-03-04 |
| 8637372 | Methods for fabricating a FINFET integrated circuit on a bulk silicon substrate | Xiaodong Yang, Jinping Liu | 2014-01-28 |
| 8557668 | Method for forming N-shaped bottom stress liner | Xiaodong Yang, Vara Govindeswara Reddy Vakada, Jinping Liu, Min Dai | 2013-10-15 |
| 7995386 | Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb | Yuji Mizuguchi, Mark Randolph, Darlene Hamilton, Yi He, Zhizheng Liu +9 more | 2011-08-09 |