Issued Patents All Time
Showing 326–350 of 399 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9496280 | Semiconductor structure having logic region and analog region | Bingwu Liu, Xusheng Wu | 2016-11-15 |
| 9496133 | Method to prevent lateral epitaxial growth in semiconductor devices by performing nitridation process on exposed Fin ends | Balasubramanian Pranatharthiharan | 2016-11-15 |
| 9478625 | Metal resistor using FinFET-based replacement gate process | Min-hwa Chi, Huang Liu | 2016-10-25 |
| 9472574 | Ultrathin body (UTB) FinFET semiconductor structure | — | 2016-10-18 |
| 9472572 | Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins | — | 2016-10-18 |
| 9462418 | Augmentation of call data information to determine a location of a wireless communication device | Kosol Jintaseranee, Mark Evans, Sara Gatmir-Motahari | 2016-10-04 |
| 9460996 | Integrated device with inductive and capacitive portions and fabrication methods | Min-hwa Chi | 2016-10-04 |
| 9443944 | Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods | Balasubramanian Pranatharthiharan | 2016-09-13 |
| 9443931 | Fabricating stacked nanowire, field-effect transistors | Guillaume Bouche, Gabriel Padron Wells | 2016-09-13 |
| 9443775 | Lithography process monitoring of local interconnect continuity | Hyun-Jin Cho, Tenko Yamashita, Chun-Chen Yeh | 2016-09-13 |
| 9443738 | Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods | Balasubramanian Pranatharthiharan | 2016-09-13 |
| 9431303 | Contact liners for integrated circuits and fabrication methods thereof | — | 2016-08-30 |
| 9431396 | Single diffusion break with improved isolation and process window and reduced cost | Bingwu Liu | 2016-08-30 |
| 9425252 | Process for single diffusion break with simplified process | Bingwu Liu | 2016-08-23 |
| 9425108 | Method to prevent lateral epitaxial growth in semiconductor devices | Balasubramanian Pranatharthiharan | 2016-08-23 |
| 9425129 | Methods for fabricating conductive vias of circuit structures | Bingwu Liu, Dingyou Zhang | 2016-08-23 |
| 9412659 | Semiconductor structure having source/drain gouging immunity | — | 2016-08-09 |
| 9401362 | Multiple threshold voltage semiconductor device | — | 2016-07-26 |
| 9356047 | Integrated circuits with self aligned contact structures for improved windows and fabrication methods | — | 2016-05-31 |
| 9355921 | Test macro for use with a multi-patterning lithography process | Tenko Yamashita, Chun-Chen Yeh, Jin Cho | 2016-05-31 |
| 9344990 | Device location accuracy metrics for applications on wireless communication devices | Soshant Bali, Sara Gatmir-Motahari | 2016-05-17 |
| 9337197 | Semiconductor structure having FinFET ultra thin body and methods of fabrication thereof | Bingwu Liu | 2016-05-10 |
| 9331202 | Replacement gate structure on FinFET devices with reduced size fin in the channel region | Bingwu Liu | 2016-05-03 |
| 9324352 | Location association identification between wireless communication devices | Phyllis Reuther | 2016-04-26 |
| 9324713 | Eliminating field oxide loss prior to FinFET source/drain epitaxial growth | Hong Yu, Bingwu Liu, Lun Zhao | 2016-04-26 |