Issued Patents All Time
Showing 176–196 of 196 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8674332 | RRAM device with an embedded selector structure and methods of making same | Eng Huat Toh, Elgin Quek | 2014-03-18 |
| 8647937 | Deep depleted channel MOSFET with minimized dopant fluctuation and diffusion levels | Eng Huat Toh | 2014-02-11 |
| 8647946 | Control gate | Lee-Wee Teo, Chunshan Yin | 2014-02-11 |
| 8536558 | RRAM structure with improved memory margin | Eng Huat Toh, Elgin Quek | 2013-09-17 |
| 8530310 | Memory cell with improved retention | Lee-Wee Teo, Chunshan Yin, Chung Foong Tan, Jae Gon Lee, Elgin Quek +1 more | 2013-09-10 |
| 8446779 | Non-volatile memory using pyramidal nanocrystals as electron storage elements | Elgin Quek, Chunshan Yin, Jae Gon Lee, Chung Foong Tan | 2013-05-21 |
| 8368127 | Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current | Ming Zhu, Eng Huat Toh, Elgin Quek | 2013-02-05 |
| 8324031 | Diffusion barrier and method of formation thereof | Lee-Wee Teo, Yung Fu Chong, Elgin Quek, Sanford Chu | 2012-12-04 |
| 8288800 | Hybrid transistor | Ming Zhu, Chun Shan Yin, Elgin Quek | 2012-10-16 |
| 8274115 | Hybrid orientation substrate with stress layer | Lee-Wee Teo, Chung Woh Lai, Johnny Widodo, Shailendra Mishra, Zhao Lun +2 more | 2012-09-25 |
| 8211761 | Semiconductor system using germanium condensation | Yung Fu Chong, Lee-Wee Teo | 2012-07-03 |
| 8138053 | Method of forming source and drain of field-effect-transistor and structure thereof | Henry K. Utomo, Shailendra Mishra, Lee-Wee Teo, Jae Gon Lee | 2012-03-20 |
| 8053327 | Method of manufacture of an integrated circuit system with self-aligned isolation structures | Shailendra Mishra, Lee-Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai +2 more | 2011-11-08 |
| 7999300 | Memory cell structure and method for fabrication thereof | Zhao Lun, James Yong Meng Lee, Lee-Wee Teo, Chung Woh Lai, Johnny Widodo +2 more | 2011-08-16 |
| 7998835 | Strain-direct-on-insulator (SDOI) substrate and method of forming | Lee-Wee Teo, Chung Foong Tan, Elgin Quek | 2011-08-16 |
| 7935589 | Enhanced stress for transistors | Lee-Wee Teo, Jae Gon Lee, Elgin Quek | 2011-05-03 |
| 7932178 | Integrated circuit having a plurality of MOSFET devices | Lee-Wee Teo, Yong Meng Lee, Jeffrey Chee, Chung Woh Lai, Johnny Widodo +2 more | 2011-04-26 |
| 7795104 | Method for fabricating device structures having a variation in electrical conductivity | Elgin Quek, Lee-Wee Teo | 2010-09-14 |
| 7562318 | Test structure for automatic dynamic negative-bias temperature instability testing | Chew Hoe Ang, Gang Chen | 2009-07-14 |
| 7132878 | Charge pump current source | Tupei Chen, Chew Hoe Ang, Jia Zhen Zheng | 2006-11-07 |
| 7103861 | Test structure for automatic dynamic negative-bias temperature instability testing | Chew Hoe Ang, Gang Chen | 2006-09-05 |