Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7489517 | Die down semiconductor package | — | 2009-02-10 |
| 7239024 | Semiconductor package with recess for die | — | 2007-07-03 |
| 6882045 | Multi-chip module and method for forming and method for deplating defective capacitors | Mark Thomas McCormack, Wen-chou Vincent Wang | 2005-04-19 |
| 6845184 | Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making | Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William T. Chou +3 more | 2005-01-18 |
| 6690845 | Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making | Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William T. Chou +3 more | 2004-02-10 |
| 6611635 | Opto-electronic substrates with electrical and optical interconnections and methods for making | Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William T. Chou +3 more | 2003-08-26 |
| 6448106 | Modules with pins and methods for making modules with pins | Wen-chou Vincent Wang, Yasuhito Takahashi, Lei Zhang | 2002-09-10 |
| 6380001 | Flexible pin count package for semiconductor device | Byoung-Youl Min | 2002-04-30 |
| 6343171 | Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making | Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William T. Chou +3 more | 2002-01-29 |
| 6326555 | Method and structure of z-connected laminated substrate for high density electronic packaging | Mark Thomas McCormack, Hunt Hang Jiang, Solomon I. Beilin | 2001-12-04 |
| 6271107 | Semiconductor with polymeric layer | Mark Thomas McCormack, Hunt Hang Jiang | 2001-08-07 |
| 6163957 | Multilayer laminated substrates with high density interconnects and methods of making the same | Hunt Hang Jiang, Mark Thomas McCormack, Michael G. Lee | 2000-12-26 |
| 5947751 | Production and test socket for ball grid array semiconductor package | — | 1999-09-07 |
| 5587336 | Bump formation on yielded semiconductor dies | Tsing-Chow Wang, Serena M. Luo, Marlita F. Macaraeg, Francisca Tung | 1996-12-24 |
| 5561328 | Photo-definable template for semiconductor chip alignment | William Loh | 1996-10-01 |
| 5420460 | Thin cavity down ball grid array package based on wirebond technology | — | 1995-05-30 |
| 5413964 | Photo-definable template for semiconductor chip alignment | William Loh | 1995-05-09 |