Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9129883 | Package structure of optical transceiver component | Yun-Cheng Huang, Chien-Wen Lu, Chung-Hsin Fu, Chi-Min Ting | 2015-09-08 |
| 8721194 | Optical transceiver module | Yun-Cheng Huang, Chi-Min Ting, Chung-Hsin Fu | 2014-05-13 |
| 7875505 | Multi-die semiconductor package structure and method for manufacturing the same | — | 2011-01-25 |
| 7838411 | Fluxless reflow process for bump formation | Runling Li | 2010-11-23 |
| 7816787 | Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes | — | 2010-10-19 |
| 7462556 | Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes | — | 2008-12-09 |
| 7381636 | Planar bond pad design and method of making the same | — | 2008-06-03 |
| 7053490 | Planar bond pad design and method of making the same | — | 2006-05-30 |
| 6784089 | Flat-top bumping structure and preparation method | Kuolung Lei, Tony Shen, Susana Samoranos, Te-Sung Wu | 2004-08-31 |
| 6674173 | Stacked paired die package and method of making the same | — | 2004-01-06 |
| 6635585 | Method for forming patterned polyimide layer | Nguyen Khe | 2003-10-21 |
| 6544878 | Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties | — | 2003-04-08 |
| 6448171 | Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability | Te-Sung Wu | 2002-09-10 |
| 6424037 | Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball | Chung W. Ho | 2002-07-23 |
| 6362087 | Method for fabricating a microelectronic fabrication having formed therein a redistribution structure | Te-Sung Wu, Erh-Kong Chieh | 2002-03-26 |
| 6316831 | Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties | — | 2001-11-13 |
| 6281041 | Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball | Chung W. Ho | 2001-08-28 |
| 5587336 | Bump formation on yielded semiconductor dies | Serena M. Luo, Marlita F. Macaraeg, Francisca Tung, Thomas J. Massingill | 1996-12-24 |
| 5414299 | Semi-conductor device interconnect package assembly for improved package performance | Louis H. Liang | 1995-05-09 |
| 5386141 | Leadframe having one or more power/ground planes without vias | Louis H. Liang | 1995-01-31 |
| 5171712 | Method of constructing termination electrodes on yielded semiconductor die by visibly aligning the die pads through a transparent substrate | Louis H. Liang | 1992-12-15 |
| 4559459 | High gain non-linear threshold input Josephson junction logic circuit | Richard M. Josephs | 1985-12-17 |
| 4509146 | High density Josephson junction memory circuit | Richard M. Josephs | 1985-04-02 |
| 4501975 | Josephson junction latch circuit | Richard M. Josephs | 1985-02-26 |
| 4458160 | High gain Josephson junction voltage amplifier | Richard M. Josephs | 1984-07-03 |