Issued Patents All Time
Showing 51–65 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7582519 | Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction | Christopher Boguslaw Kocon | 2009-09-01 |
| 7504303 | Trench-gate field effect transistors and methods of forming the same | Hamza Yilmaz, Daniel Calafut, Christopher Boguslaw Kocon, Steven Sapp, Dean E. Probst +5 more | 2009-03-17 |
| 7416948 | Trench FET with improved body to gate alignment | Nathan Kraft, Ashok Challa, Steven Sapp, Hamza Yilmaz, Daniel Calafut +5 more | 2008-08-26 |
| 7230313 | Voltage divider field plate termination with unequal fixed biasing | Dwayne S. Reichl, Bernard J. Czeck, Douglas Lange | 2007-06-12 |
| 7132712 | Trench structure having one or more diodes embedded therein adjacent a PN junction | Christopher Boguslaw Kocon | 2006-11-07 |
| 7118951 | Method of isolating the current sense on power devices while maintaining a continuous stripe cell | Dwayne S. Reichl, Douglas Lange | 2006-10-10 |
| 6906362 | Method of isolating the current sense on power devices while maintaining a continuous stripe cell | Dwayne S. Reichl, Douglas Lange | 2005-06-14 |
| 6831329 | Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off | Jon Gladish, Sampat Shekhawat, Gary M. Dolny, Praveen Muraleedharan Shenoy, Douglas Lange +1 more | 2004-12-14 |
| 6798019 | IGBT with channel resistors | Dwayne S. Reichl, Jack Edward Wojslawowicz, Bernard J. Czeck, Robert D. Baran, Douglas Lange | 2004-09-28 |
| 6777747 | Thick buffer region design to improve IGBT self-clamped inductive switching (SCIS) energy density and device manufacturability | Jack Edward Wojslawowicz, Bernard J. Czeck, Robert D. Baran, Douglas Lange | 2004-08-17 |
| 5872028 | Method of forming power semiconductor devices with controllable integrated buffer | Anup Bhalla, Jeffrey Webster, Joseph L. Cumbo | 1999-02-16 |
| 5323036 | Power FET with gate segments covering drain regions disposed in a hexagonal pattern | John Manning Savidge Neilson, Frederick P. Jones, Christopher L. Rexer | 1994-06-21 |
| 5218220 | Power FET having reduced threshold voltage | John Manning Savidge Neilson, Frederick P. Jones | 1993-06-08 |
| 5164802 | Power VDMOSFET with schottky on lightly doped drain of lateral driver FET | Frederick P. Jones, John Manning Savidge Neilson, Robert S. Wrathall, Jeffrey G. Mansmann, Claire E. Jackoski | 1992-11-17 |
| 5079608 | Power MOSFET transistor circuit with active clamp | Paul J. Wodarczyk, Frederick P. Jones, John Manning Savidge Neilson | 1992-01-07 |