Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6489191 | Method for forming self-aligned channel implants using a gate poly reverse mask | Kai Shao, Yimin Wang, Jian Xun Li | 2002-12-03 |
| 6410394 | Method for forming self-aligned channel implants using a gate poly reverse mask | Kai Shao, Yimin Wang, Jian Xun Li | 2002-06-25 |
| 6372652 | Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage | Purakh Raj Verma, Zia A. Shafi, Yu Shan, ZENG-MAO ZHENG, Manju Sarkar | 2002-04-16 |
| 6297132 | Process to control the lateral doping profile of an implanted channel region | Jiong Zhang, Kai Shao | 2001-10-02 |
| 6291307 | Method and structure to make planar analog capacitor on the top of a STI structure | Yang Pan, Wang Yimin, Kai Shao | 2001-09-18 |
| 6284590 | Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors | Randall Cher Liang Cha, Cheng Yeow Ng, Tae Jong Lee, Chua Chee Tee | 2001-09-04 |
| 6284594 | Formation of an interpoly capacitor structure using a chemical mechanical polishing procedure | Yong Ju, Kai Shao, Yimin Wang | 2001-09-04 |
| 6159759 | Method to form liquid crystal displays using a triple damascene technique | Kai Shao, Cerdin Lee, Yi Xu | 2000-12-12 |
| 6156602 | Self-aligned precise high sheet RHO register for mixed-signal application | Kai Shao, Cerdin Lee | 2000-12-05 |
| 6133079 | Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions | Min Zhu, Kai Shao | 2000-10-17 |
| 6124194 | Method of fabrication of anti-fuse integrated with dual damascene process | Kai Shao, Yi Xu, Cerdin Lee | 2000-09-26 |
| 6117747 | Integration of MOM capacitor into dual damascene process | Kai Shao, Yi Xu, Cerdin Lee | 2000-09-12 |
| 5874764 | Modular MOSFETS for high aspect ratio applications | Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Louis L. Hsu | 1999-02-23 |
| 5721144 | Method of making trimmable modular MOSFETs for high aspect ratio applications | Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Louis L. Hsu | 1998-02-24 |
| 5521399 | Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit | Chang-Ming Hsieh, Louis L. Hsu, Kyong-Min Kim, Shaw-Ning Mei | 1996-05-28 |
| 5484738 | Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits | Chang-Ming Hsieh, Louis L. Hsu, Kyong-Min Kim, Shaw-Ning Mei | 1996-01-16 |
| 5331199 | Bipolar transistor with reduced topography | Kyong-Min Kim, Shaw-Ning Mei, Victor R. Nastasi, Somnuk Ratanaphanyarat | 1994-07-19 |
| 5266505 | Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors | David C. Ahlgren, Mary J. Saccamango, David Sunderland, Tze-Chiang Chen | 1993-11-30 |
| 5234846 | Method of making bipolar transistor with reduced topography | Kyong-Min Kim, Mei Shaw-Ning, Victor R. Nastasi, Somnuk Ratanaphanyarat | 1993-08-10 |
| 5229322 | Method of making low resistance substrate or buried layer contact | Kyong-Min Kim, Shaw-Ning Mei, Mary J. Saccamango, Donald R. Vigliotti, deceased, Robert J. von Gutfeld | 1993-07-20 |
| 5015594 | Process of making BiCMOS devices having closely spaced device regions | San-Mei Ku, Russell C. Lange, Joseph F. Shephard, Paul J. Tsang, Wen-Yuan Wang | 1991-05-14 |
| 4385975 | Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate | Allen P. Ho, Cheng T. Horng, Bernard M. Kemlage | 1983-05-31 |