Issued Patents All Time
Showing 126–150 of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6678840 | Fault containment and error recovery in a scalable multiprocessor | Peter J. Bannon, Kourosh Gharachorloo, Thukalan V. Verghese | 2004-01-13 |
| 6668335 | System for recovering data in a multiprocessor system comprising a conduction path for each bit between processors where the paths are grouped into separate bundles and routed along different paths | Scott E. Breach, John Eble, Arvind Kumar, Darrel D. Donaldson, David W. Hartwell | 2003-12-23 |
| 6662319 | Special encoding of known bad data | David A. Webb, Steve Lang | 2003-12-09 |
| 6662265 | Mechanism to track all open pages in a DRAM memory system | Maurice B. Steinman, Michael Bertone, Peter J. Bannon, Gregg A. Bouchard | 2003-12-09 |
| 6654858 | Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol | David Asher, Brian P. Lilly, Michael Bertone | 2003-11-25 |
| 6651144 | Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state | Rahul Razdan, James B. Keller | 2003-11-18 |
| 6636955 | Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature | Peter J. Bannon, Maurice B. Steinman, Scott E. Breach, Allen J. Baum, Gregg A. Bouchard | 2003-10-21 |
| 6633960 | Scalable directory based cache coherence protocol | Kourosh Gharachorloo, David Asher | 2003-10-14 |
| 6622225 | System for minimizing memory bank conflicts in a computer system | Michael Bertone, Michael C. Braganza, Gregg A. Bouchard, Maurice B. Steinman | 2003-09-16 |
| 6567900 | Efficient address interleaving with simultaneous multiple locality options | — | 2003-05-20 |
| 6546453 | Proprammable DRAM address mapping mechanism | Maurice B. Steinman, Peter J. Bannon, Michael C. Braganza, Gregg A. Bouchard | 2003-04-08 |
| 6493802 | Method and apparatus for performing speculative memory fills into a microprocessor | Rahul Razdan, James B. Keller | 2002-12-10 |
| 6463523 | Method and apparatus for delaying the execution of dependent loads | Rahul Razdan, Edward J. McLellan | 2002-10-08 |
| 6397302 | Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system | Rahul Razdan, James B. Keller | 2002-05-28 |
| 6349366 | Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commands | Rahul Razdan, James B. Keller | 2002-02-19 |
| 6314496 | Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commands | Rahul Razdan, James B. Keller | 2001-11-06 |
| 6295583 | Method and apparatus for resolving probes in multi-processor systems which do not use external duplicate tags for probe filtering | Rahul Razdan, Solomon J. Katzman, James B. Keller | 2001-09-25 |
| 6253285 | Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing | Rahul Razdan, James B. Keller | 2001-06-26 |
| 6216174 | System and method for fast barrier synchronization | Steven L. Scott | 2001-04-10 |
| 6199153 | Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements | Rahul Razdan, Solomon J. Katzman, James B. Keller | 2001-03-06 |
| 6163821 | Method and apparatus for balancing load vs. store access to a primary data cache | James B. Keller, Stephen C. Root, Paul Geoffrey Lowney | 2000-12-19 |
| 6029212 | Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers | Steven M. Oberlin, Steven L. Scott, Eric C. Fromm | 2000-02-22 |
| 5864738 | Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller | Steven M. Oberlin, Steven L. Scott | 1999-01-26 |
| 5841973 | Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory | Steven M. Oberlin, Steven L. Scott | 1998-11-24 |
| 5835925 | Using external registers to extend memory reference capabilities of a microprocessor | Steven M. Oberlin, Steven L. Scott, Eric C. Fromm | 1998-11-10 |