Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
KH

Kenlin Huang — 10 Patents

HTHeadway Technologies: 3 patents #155 of 309Top 55%
UMUnited Microelectronics: 3 patents #1,523 of 4,560Top 35%
Applied Materials: 3 patents #3,025 of 7,310Top 45%
Lam Research: 1 patents #1,379 of 2,128Top 65%
Milpitas, CA: #519 of 3,192 inventorsTop 20%
California: #61,378 of 386,348 inventorsTop 20%
Overall (All Time): #481,000 of 4,157,543Top 15%
10 Patents All Time
Kenlin Huang has been granted 10 US patents while listed as an inventor at Applied Materials. The first was granted in 1998 and the most recent in January 2015. Kenlin Huang ranks #481,000 of 4,157,543 US inventors in our database (top 11.6%). Patent records list Kenlin Huang in Milpitas, CA, US.

Patents per Year

Patents granted per year, 1998 to 2015Bar chart with a peak of 2 patents in 2003.peak 21998: 1 patents19982003: 2 patents20032007: 2 patents20072008: 1 patents20082011: 1 patents20112014: 2 patents20142015: 1 patents2015

Issued Patents All Time

Showing 1–10 of 10 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8933542 Method to reduce magnetic film stress for better yield Tom Zhong, Chyu-Jiuh Torng 2015-01-13
8803293 Method to reduce magnetic film stress for better yield Tom Zhong, Chyu-Jiuh Torng 2014-08-12
8772051 Fabrication method for embedded magnetic memory Tom Zhong, Chyu-Jiuh Torng 2014-07-08
7972959 Self aligned double patterning flow with non-sacrificial features Bencherki Mebarki, Li Yan Miao 2011-07-05 $5,297,000
7408212 Stackable resistive cross-point memory with schottky diode isolation Harry Luan, Jein-Chen Young, Arthur Wang, Kai-Cheng Chou 2008-08-05 $1,444,000
7186658 Method and resulting structure for PCMO film to obtain etching rate and mask to selectively by inductively coupled plasma Kaicheng Chou, Harry Luan, Jein-Chen Young, Arthur Wang 2007-03-06 $1,552,000
7172939 Method and structure for fabricating non volatile memory arrays Kai-Cheng Chou, Harry Laun, J.C. Young, Arthur Wang 2007-02-06 $1,016,000
6638874 Methods used in fabricating gates in integrated circuit device structures Sang In Yi, Seowoo Nam, Padmapani Nallan 2003-10-28 $43,198,000
6635577 Method for reducing topography dependent charging effects in a plasma enhanced semiconductor wafer processing system John M. Yamartino, Peter K. Loewengardt, Diana Xiaobing Ma 2003-10-21 $27,123,000
5827437 Multi-step metallization etch Richard Yang 1998-10-27 $9,432,000