Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9373548 | CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer | Gen Pei, Scott Luning | 2016-06-21 |
| 9231079 | Stress memorization techniques for transistor devices | Cuiqin Xu, Isabelle Ferain | 2016-01-05 |
| 9178053 | Transistor device with improved source/drain junction architecture and methods of making such a device | Jerome Ciavatti | 2015-11-03 |
| 9136330 | Shallow trench isolation | Yanxiang Liu, Xiaodong Yang, Manfred Eller | 2015-09-15 |
| 9082698 | Methods to improve FinFet semiconductor device behavior using co-implantation under the channel region | Manoj Joshi, Manfred Eller | 2015-07-14 |
| 9034737 | Epitaxially forming a set of fins in a semiconductor device | Michael Hargrove, Christian Gruensfelder, Yanxiang Liu, Srikanth B. Samavedam | 2015-05-19 |
| 8962441 | Transistor device with improved source/drain junction architecture and methods of making such a device | Jerome Ciavatti | 2015-02-24 |
| 8846476 | Methods of forming multiple N-type semiconductor devices with different threshold voltages on a semiconductor substrate | Yanxiang Liu, Manfred Eller | 2014-09-30 |
| 7745296 | Raised source and drain process with disposable spacers | Huicai Zhong | 2010-06-29 |
| 7442601 | Stress enhanced CMOS circuits and methods for their fabrication | Gen Pei, Scott Luning | 2008-10-28 |
| 7329599 | Method for fabricating a semiconductor device | Frank Wirbeleit, Tibor Bolom | 2008-02-12 |