HG

Hans-Joachim L. Gossmann

Applied Materials: 12 patents #1,120 of 7,310Top 20%
AT AT&T: 7 patents #2,615 of 18,772Top 15%
VA Varian Semiconductor Equipment Associates: 4 patents #157 of 513Top 35%
AG Agere Systems Guardian: 2 patents #139 of 810Top 20%
AS Agere Systems: 1 patents #984 of 1,849Top 55%
Overall (All Time): #149,599 of 4,157,543Top 4%
26
Patents All Time

Issued Patents All Time

Showing 1–25 of 26 patents

Patent #TitleCo-InventorsDate
12381088 Method for precision oxidation control by ion implantation Supakit Charnvanichborikarn, Cao-Minh Vincent Lu, Ana Cristina Gomez Herrero, Wei Zou, Andrew Waite 2025-08-05
12247283 Method and apparatus for controlled ion implantation Alexander Eidukonis, Dennis Rodier, Stanislav S. Todorov, Richard M. White, Wei Zhao +2 more 2025-03-11
12002852 System and technique for creating implanted regions using multiple tilt angles Venkataramana R. Chavva 2024-06-04
11830739 Techniques to increase CMOS image sensor well depth by cyrogenic ion channeling of ultra high energy ions Stanislav S. Todorov, Hiroyuki Ito 2023-11-28
11804537 Channeled implants for SiC MOSFET fabrication Qintao Zhang, Samphy Hong, Wei Zou 2023-10-31
11699570 System and method for hi-precision ion implantation Supakit Charnvanichborikarn, Wei Zou, Qintao Zhang, Aseem K. Srivastava, William R. Bogiages, Jr. +1 more 2023-07-11
11551904 System and technique for profile modulation using high tilt angles Venkataramana R. Chavva, Kyuha Shim, Edwin Arevalo, Scott Falk, Rajesh Prasad 2023-01-10
11495500 Horizontal GAA nano-wire and nano-slab transistors Benjamin Colombeau 2022-11-08
11476330 System and technique for creating implanted regions using multiple tilt angles Venkataramana R. Chavva 2022-10-18
11424125 Angled ion implant to reduce MOSFET trench sidewall roughness Qintao Zhang, Wei Zou 2022-08-23
10483355 Forming non-line-of-sight source drain extension in an NMOS FINFET using n-doped selective epitaxial growth Matthias Bauer, Benjamin Colombeau 2019-11-19
10381465 Method for fabricating asymmetrical three dimensional device Shiyu Sun, Naomi Yoshida, Benjamin Colombeau 2019-08-13
9853129 Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth Matthias Bauer, Benjamin Colombeau 2017-12-26
9748364 Method for fabricating three dimensional device Shiyu Sun, Naomi Yoshida, Benjamin Colombeau 2017-08-29
9455196 Method for improving fin isolation Nilay A. Pradhan, Benjamin Colombeau 2016-09-27
9455335 Techniques for ion implantation of non-planar field effect transistors Anthony Renau 2016-09-27
6632728 Increasing the electrical activation of ion-implanted dopants Conor S. Rafferty, Tony Haynes, Ramki Kalyanaraman, Vincent Venezia, Maria Lourdes Pelaz-Montes 2003-10-14
6403454 Silicon semiconductor devices with &dgr;-doped layers Paul H. Citrin, David Müller 2002-06-11
6358824 Integrated circuits with tub-ties and shallow trench isolation Thi-Hong-Ha Vuong 2002-03-19
6153920 Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby Conor S. Rafferty 2000-11-28
6054342 Method of making integrated circuits with tub-ties Thi-Hong-Ha Vuong 2000-04-25
6043139 Process for controlling dopant diffusion in a semiconductor layer David Eaglesham, John M. Poate, Peter Stolk 2000-03-28
5949112 Integrated circuits with tub-ties Thi-Hong-Ha Vuong 1999-09-07
5731626 Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby David Eaglesham, John M. Poate, Peter Stolk 1998-03-24
5500391 Method for making a semiconductor device including diffusion control Joze Bevk, Leonard C. Feldman, Henry S. Luftman, Ran-Hong Yan 1996-03-19