Issued Patents All Time
Showing 26–50 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8498888 | Cost-based fulfillment tie-breaking | Paul Raff | 2013-07-30 |
| 8402412 | Increasing circuit speed and reducing circuit leakage by utilizing a local surface temperature effect | Cinti X. Chen, Joe W. Zhao | 2013-03-19 |
| 8396585 | Method and system for inventory placement according to expected item picking rates | Felix F. Antony | 2013-03-12 |
| 8024064 | Placement of inventory in a materials handling facility | Kaushal A. Sanghavi, Kalyanaraman Prasad, Pradeep Desai, Han-Sen Lee, Nadia Shouraboura | 2011-09-20 |
| 7881820 | Method and system for inventory placement according to expected item picking rates | Felix F. Antony | 2011-02-01 |
| 7145344 | Method and circuits for localizing defective interconnect resources in programmable logic devices | David Mark, Yuezhen Fan, Zhi-Min Ling | 2006-12-05 |
| 7020860 | Method for monitoring and improving integrated circuit fabrication using FPGAs | Joe W. Zhao, Feng Wang, Zhi-Min Ling | 2006-03-28 |
| 6424003 | EEPROM cell with self-aligned tunneling window | Sunil Mehta, Christopher O. Schmidt | 2002-07-23 |
| 6404006 | EEPROM cell with tunneling across entire separated channels | Steven J. Fong | 2002-06-11 |
| 6369421 | EEPROM having stacked dielectric to increase programming speed | Qi Xiang | 2002-04-09 |
| 6326663 | Avalanche injection EEPROM memory cell with P-type control gate | Steven J. Fong, Sunil Mehta | 2001-12-04 |
| 6309942 | STI punch-through defects and stress reduction by high temperature oxide reflow process | Ting Tsui, Robert H. Tu, Sunil Mehta | 2001-10-30 |
| 6294811 | Two transistor EEPROM cell | Steven J. Fong | 2001-09-25 |
| 6294810 | EEPROM cell with tunneling at separate edge and channel regions | Steven J. Fong | 2001-09-25 |
| 6291327 | Optimization of S/D annealing to minimize S/D shorts in memory array | Sunil Mehta, Christopher O. Schmidt, Robert H. Tu | 2001-09-18 |
| 6274898 | Triple-well EEPROM cell using P-well for tunneling across a channel | Sunil Mehta | 2001-08-14 |
| 6261944 | Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect | Sunil Mehta | 2001-07-17 |
| 6255169 | Process for fabricating a high-endurance non-volatile memory device | Qi Xiang, Sunil Mehta | 2001-07-03 |
| 6221733 | Reduction of mechanical stress in shallow trench isolation process | Sunil Mehta, Robert H. Tu | 2001-04-24 |
| 6218245 | Method for fabricating a high-density and high-reliability EEPROM device | Qi Xiang | 2001-04-17 |
| 6207989 | Non-volatile memory device having a high-reliability composite insulation layer | Sunil Mehta | 2001-03-27 |
| 6172392 | Boron doped silicon capacitor plate | Christopher O. Schmidt, Sunil Mehta | 2001-01-09 |
| 6093946 | EEPROM cell with field-edgeless tunnel window using shallow trench isolation process | Sunil Mehta | 2000-07-25 |
| 6087696 | Stacked tunneling dielectric technology for improving data retention of EEPROM cell | Qi Xiang, Sunil Mehta | 2000-07-11 |
| 6075724 | Method for sorting semiconductor devices having a plurality of non-volatile memory cells | Sunil Mehta | 2000-06-13 |