Issued Patents All Time
Showing 51–64 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6075293 | Semiconductor device having a multi-layer metal interconnect structure | Sunil Mehta, Van-Hung Pham, Amit P. Marathe | 2000-06-13 |
| 6064105 | Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide | Radu Barsan, Sunil Mehta | 2000-05-16 |
| 6040019 | Method of selectively annealing damaged doped regions | Emi Ishida, Sunil Mehta | 2000-03-21 |
| 6009033 | Method of programming and erasing an EEPROM device under an elevated temperature and apparatus thereof | Sunil Mehta | 1999-12-28 |
| 5999449 | Two transistor EEPROM cell using P-well for tunneling across a channel | Sunil Mehta | 1999-12-07 |
| 5969992 | EEPROM cell using P-well for tunneling across a channel | Sunil Mehta | 1999-10-19 |
| 5942780 | Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate | Radu Barsan, Sunil Mehta | 1999-08-24 |
| 5904575 | Method and apparatus incorporating nitrogen selectively for differential oxide growth | Emi Ishida, Sunil Mehta | 1999-05-18 |
| 5885904 | Method to incorporate, and a device having, oxide enhancement dopants using gas immersion laser doping (GILD) for selectively growing an oxide layer | Sunil Mehta, Emi Ishida | 1999-03-23 |
| 5854114 | Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide | Radu Barsan, Sunil Mehta | 1998-12-29 |
| 5841701 | Method of charging and discharging floating gage transistors to reduce leakage current | Radu Barsan, Sunil Mehta | 1998-11-24 |
| 5795627 | Method for annealing damaged semiconductor regions allowing for enhanced oxide growth | Sunil Mehta, Emi Ishida | 1998-08-18 |
| 5761116 | V.sub.pp only scalable EEPROM memory cell having transistors with thin tunnel gate oxide | Radu Barsan | 1998-06-02 |
| 5672521 | Method of forming multiple gate oxide thicknesses on a wafer substrate | Radu Barsan, Sunil Mehta | 1997-09-30 |