Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9971923 | Fingerprint identification device and mobile terminal having same | Yixiang Qiu | 2018-05-15 |
| 9831216 | Chip packaging module | Baoquan WU | 2017-11-28 |
| 6790750 | Semiconductor-on-insulator body-source contact and method | Qi Xiang, Yowjuang W. Liu | 2004-09-14 |
| 6744101 | Non-uniform gate/dielectric field effect transistor | Yowjuang W. Liu, Don Wollesen | 2004-06-01 |
| 6608352 | Determination of thermal resistance for field effect transistor formed in SOI technology | Michael Lee | 2003-08-19 |
| 6525381 | Semiconductor-on-insulator body-source contact using shallow-doped source, and method | Qi Xiang, Yowjuang W. Liu | 2003-02-25 |
| 6441434 | Semiconductor-on-insulator body-source contact and method | Qi Xiang, Yowjuang W. Liu | 2002-08-27 |
| 6437404 | Semiconductor-on-insulator transistor with recessed source and drain | Qi Xiang, Ming-Ren Lin | 2002-08-20 |
| 6423604 | Determination of thermal resistance for field effect transistor formed in SOI technology | Michael Lee | 2002-07-23 |
| 6420770 | STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides | Qi Xiang, Ming-Ren Lin | 2002-07-16 |
| 6417556 | High K dielectric de-coupling capacitor embedded in backend interconnect | Qi Xiang | 2002-07-09 |
| 6391767 | Dual silicide process to reduce gate resistance | Carl Robert Huster, Concetta Riccobene | 2002-05-21 |
| 6373103 | Semiconductor-on-insulator body-source contact using additional drain-side spacer, and method | Qi Xiang, Yowjuang W. Liu | 2002-04-16 |
| 6323099 | High k interconnect de-coupling capacitor with damascene process | Qi Xiang | 2001-11-27 |
| 6306710 | Fabrication of a gate structures having a longer length toward the top for formation of a rectangular shaped spacer | Olov Karlsson, Bill Liu, Scott A. Bell | 2001-10-23 |
| 6274420 | Sti (shallow trench isolation) structures for minimizing leakage current through drain and source silicides | Qi Xiang, Ming-Ren Lin | 2001-08-14 |
| 6275972 | Method for accurate channel-length extraction in MOSFETs | Yowjuang W. Liu | 2001-08-14 |
| 6255219 | Method for fabricating high-performance submicron MOSFET with lateral asymmetric channel | Qi Xiang | 2001-07-03 |
| 6225669 | Non-uniform gate/dielectric field effect transistor | Yowjuang W. Liu, Don Wollesen | 2001-05-01 |
| 6169302 | Determination of parasitic capacitance between the gate and drain/source local interconnect of a field effect transistor | Qi Xiang, Yowjuang W. Liu | 2001-01-02 |
| 6168999 | Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain | Qi Xiang | 2001-01-02 |
| 6166558 | Method for measuring gate length and drain/source gate overlap | Chun Jiang, Zicheng Gary Ling, Yowjuang W. Liu | 2000-12-26 |
| 6153534 | Method for fabricating a dual material gate of a short channel field effect transistor | Qi Xiang, Yowjuang W. Liu | 2000-11-28 |
| 6069485 | C-V method to extract lateral channel doping profiles of MOSFETs | Yowjuang W. Liu, Chun Jiang | 2000-05-30 |