Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8219946 | Method for clock gating circuits | Chaiyasit Manovit, Wanlin Cao, Sridhar Narayanan | 2012-07-10 |
| 8099703 | Method and system for verifying power-optimized electronic designs using equivalency checking | Chaiyasit Manovit, Sridhar Narayanan | 2012-01-17 |
| 8086915 | Memory controller with loopback test interface | Luka Bodrozic, Sukalpa Biswas, Hao Chen, James B. Keller | 2011-12-27 |
| 8055975 | Combined single error correction/device kill detection code | Brian P. Lilly, Robert Gries, Sukalpa Biswas, Hao Chen | 2011-11-08 |
| 7991928 | Retry mechanism | James B. Keller, Ramesh Gunna | 2011-08-02 |
| 7970970 | Non-blocking address switch with shallow per agent queues | James B. Keller, Ruchi Wadhawan, George Kong Yiu, Ramesh Gunna | 2011-06-28 |
| 7949832 | Latency reduction for cache coherent bus-based cache | Brian P. Lilly, Ramesh Gunna | 2011-05-24 |
| 7836324 | Oversampling-based scheme for synchronous interface communication | Sukalpa Biswas, Vincent R. von Kaenel, Priya Ananthanarayanan | 2010-11-16 |
| 7836372 | Memory controller with loopback test interface | Luka Bodrozic, Sukalpa Biswas, Hao Chen, James B. Keller | 2010-11-16 |
| 7752366 | Non-blocking address switch with shallow per agent queues | James B. Keller, Ruchi Wadhawan, George Kong Yiu, Ramesh Gunna | 2010-07-06 |
| 7746116 | Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis | Sridhar Narayanan, Chaiyasit Manovit, Gerald Gras | 2010-06-29 |
| 7702858 | Latency reduction for cache coherent bus-based cache | Brian P. Lilly, Ramesh Gunna | 2010-04-20 |
| 7586911 | Method and apparatus for packet transmit queue control | Wei-Han Lien, Brian Hang Wai Yang | 2009-09-08 |
| 7529866 | Retry mechanism in cache coherent communication among agents | James B. Keller, Ramesh Gunna | 2009-05-05 |
| 7471682 | Method and apparatus for providing internal table extensibility based on product configuration | Gaurav Singh, Ali Kani, Kiran B. Kattel, Brian Hang Wai Yang | 2008-12-30 |
| 7461190 | Non-blocking address switch with shallow per agent queues | James B. Keller, Ruchi Wadhawan, George Kong Yiu, Ramesh Gunna | 2008-12-02 |
| 7426601 | Segmented interconnect for connecting multiple agents in a system | James B. Keller, George Kong Yiu, Ruchi Wadhawan | 2008-09-16 |
| 7398361 | Combined buffer for snoop, store merging, load miss, and writeback operations | Ramesh Gunna, Po-Yung Chang, James B. Keller, Tse-Yuh Yeh | 2008-07-08 |
| 7269682 | Segmented interconnect for connecting multiple agents in a system | James B. Keller, George Kong Yiu, Ruchi Wadhawan | 2007-09-11 |
| 6741258 | Distributed translation look-aside buffers for graphics address remapping table | John C. Peck, Scott Waldron | 2004-05-25 |
| 6686920 | Optimizing the translation of virtual addresses into physical addresses using a pipeline implementation for least recently used pointer | John C. Peck, Scott Waldron | 2004-02-03 |
| 6624681 | Circuit and method for stopping a clock tree while maintaining PLL lock | Bruce A. Loyer, Michael S. Quimby, Niranjan Venigandla | 2003-09-23 |
| 6601182 | Optimized static sliding-window for ACK sampling | John C. Peck | 2003-07-29 |
| 6571318 | Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism | Benjamin T. Sander, William A. Hughes, Teik-Chung Tan | 2003-05-27 |
| 6449759 | System and method for automatic insertion and placement of repeater buffers on an integrated circuit floor plan | Mark G. Whitney | 2002-09-10 |