Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9535627 | Latency-aware memory control | David A. Roberts | 2017-01-03 |
| 9472299 | Methods and systems for mitigating memory drift | David A. Roberts | 2016-10-18 |
| 9377954 | System and method for memory allocation in a multiclass memory system | Gabriel H. Loh, Mitesh R. Meswani, Mark Richard Nutter | 2016-06-28 |
| 9344091 | Die-stacked memory device with reconfigurable logic | Nuwan Jayasena, Michael Schulte, Gabriel H. Loh | 2016-05-17 |
| 9235528 | Write endurance management techniques in the logic layer of a stacked memory | Lisa R. Hsu, Gabriel H. Loh, Michael Schulte, Nuwan Jayasena, James M. O'Connor | 2016-01-12 |
| 9201777 | Quality of service support using stacked memory device with logic die | Lisa R. Hsu, Gabriel H. Loh, Bradford M. Beckmann | 2015-12-01 |
| 9170948 | Cache coherency using die-stacked memory device with logic die | Gabriel H. Loh, Bradford M. Beckmann, Lisa R. Hsu, Michael Schulte | 2015-10-27 |
| 9135185 | Die-stacked memory device providing data translation | Gabriel H. Loh, Bradford M. Beckmann, James M. O'Connor, Michael Schulte, Lisa R. Hsu +1 more | 2015-09-15 |
| 8922243 | Die-stacked memory device with reconfigurable logic | Nuwan Jayasena, Michael Schulte, Gabriel H. Loh | 2014-12-30 |
| 8879301 | Method and apparatus for controlling state information retention in an apparatus | David E. Mayhew, Mark Hummel | 2014-11-04 |
| 8806182 | Multiple-core processor supporting multiple instruction set architectures | James Walter Rymarczyk, Thomas J. Heller, Jr. | 2014-08-12 |
| 8686559 | Semiconductor chip stacking for redundancy and yield improvement | Kerry Bernstein, Philip G. Emma | 2014-04-01 |
| 8597960 | Semiconductor chip stacking for redundancy and yield improvement | Kerry Bernstein, Philip G. Emma | 2013-12-03 |
| 8122216 | Systems and methods for masking latency of memory reorganization work in a compressed memory system | David M. Daly, Peter A. Franaszek, Luis A. Lastras-Montano, Michael R. Trombley | 2012-02-21 |
| 8028290 | Multiple-core processor supporting multiple instruction set architectures | James Walter Rymarczyk, Thomas J. Heller, Jr. | 2011-09-27 |
| 7668096 | Apparatus for modeling queueing systems with highly variable traffic arrival rates | Noshir Cavas Wadia | 2010-02-23 |
| 7647519 | System and computer program product for dynamically managing power in microprocessor chips according to present processing demands | Thomas J. Heller, Jr., Bernard S. Meyerson, James Walter Rymarczyk | 2010-01-12 |
| 7484043 | Multiprocessor system with dynamic cache coherency regions | Thomas J. Heller, Jr., Richard I. Baum, James Walter Rymarczyk | 2009-01-27 |
| 7401240 | Method for dynamically managing power in microprocessor chips according to present processing demands | Thomas J. Heller, Jr., Bernard S. Meyerson, James Walter Rymarczyk | 2008-07-15 |
| 7376083 | Apparatus and method for modeling queueing systems with highly variable traffic arrival rates | Noshir Cavas Wadia | 2008-05-20 |
| 7099816 | Method, system and article of manufacture for an analytic modeling technique for handling multiple objectives | Noshir Cavas Wadia, Peng Ye | 2006-08-29 |
| 6768968 | Method and system of an integrated simulation tool using business patterns and scripts | Noshir Cavas Wadia | 2004-07-27 |
| 6457100 | Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls | Thomas J. Heller, Jr., Gottfried Andreas Goldiran | 2002-09-24 |
| 5895487 | Integrated processing and L2 DRAM cache | William T. Boyd, Thomas J. Heller, Jr., Richard E. Matick, Stanley E. Schuster | 1999-04-20 |
| 5875470 | Multi-port multiple-simultaneous-access DRAM chip | Jeffrey H. Dreibelbis, Wayne F. Ellis, Thomas J. Heller, Jr., Howard L. Kalter, David Meltzer | 1999-02-23 |