Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6140190 | Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors | Mark I. Gardner, Thomas E. Spikes, Jr. | 2000-10-31 |
| 6111298 | Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length | Mark I. Gardner, Daniel Kadosh | 2000-08-29 |
| 6104069 | Semiconductor device having an elevated active region formed in an oxide trench | Daniel Kadosh, Mark I. Gardner | 2000-08-15 |
| 6104064 | Asymmetrical transistor structure | Daniel Kadosh, Mark I. Gardner, Jon D. Cheek, Fred N. Hause, Robert Dawson +1 more | 2000-08-15 |
| 6091118 | Semiconductor device having reduced overlap capacitance and method of manufacture thereof | — | 2000-07-18 |
| 6077748 | Advanced trench isolation fabrication scheme for precision polysilicon gate control | Mark I. Gardner, Daniel Kadosh | 2000-06-20 |
| 6075258 | Elevated transistor fabrication technique | Mark I. Gardner, Daniel Kadosh | 2000-06-13 |
| 6069046 | Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment | Mark I. Gardner, Daniel Kadosh | 2000-05-30 |
| 6040220 | Asymmetrical transistor formed from a gate conductor of unequal thickness | Mark I. Gardner, Daniel Kadosh | 2000-03-21 |
| 6030875 | Method for making semiconductor device having nitrogen-rich active region-channel interface | Charles E. May, Robert Dawson | 2000-02-29 |
| 6030860 | Elevated substrate formation and local interconnect integrated fabrication | Mark I. Gardner, Daniel Kadosh | 2000-02-29 |
| 6027964 | Method of making an IGFET with a selectively doped gate in combination with a protected resistor | Mark I. Gardner, Daniel Kadosh | 2000-02-22 |
| 6027978 | Method of making an IGFET with a non-uniform lateral doping profile in the channel region | Mark I. Gardner, Daniel Kadosh | 2000-02-22 |
| 6008096 | Ultra short transistor fabrication method | Mark I. Gardner, Daniel Kadosh | 1999-12-28 |
| 6004849 | Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source | Mark I. Gardner, Daniel Kadosh | 1999-12-21 |
| 5970349 | Semiconductor device having one or more asymmetric background dopant regions and method of manufacture thereof | Jon Cheek, Mark I. Gardner | 1999-10-19 |
| 5963809 | Asymmetrical MOSFET with gate pattern after source/drain formation | Mark I. Gardner | 1999-10-05 |
| 5959337 | Air gap spacer formation for high performance MOSFETs | Mark I. Gardner, Daniel Kadosh | 1999-09-28 |
| 5949092 | Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator | Daniel Kadosh, Mark I. Gardner | 1999-09-07 |
| 5943562 | Semiconductor fabrication employing a transistor gate coupled to a localized substrate | Mark I. Gardner, Daniel Kadosh | 1999-08-24 |
| 5940707 | Vertically integrated advanced transistor formation | Mark I. Gardner | 1999-08-17 |
| 5898189 | Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method | Mark I. Gardner, Daniel Kadosh | 1999-04-27 |
| 5888853 | Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof | Mark I. Gardner, Daniel Kadosh | 1999-03-30 |
| 5885761 | Semiconductor device having an elevated active region formed from a thick polysilicon layer and method of manufacture thereof | Daniel Kadosh, Mark I. Gardner | 1999-03-23 |
| 5872038 | Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof | Daniel Kadosh, Mark I. Gardner | 1999-02-16 |