Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5869379 | Method of forming air gap spacer for high performance MOSFETS' | Mark I. Gardner, Daniel Kadosh | 1999-02-09 |
| 5854115 | Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length | Mark I. Gardner, Daniel Kadosh | 1998-12-29 |
| 5834350 | Elevated transistor fabrication technique | Mark I. Gardner, Daniel Kadosh | 1998-11-10 |
| 5804496 | Semiconductor device having reduced overlap capacitance and method of manufacture thereof | — | 1998-09-08 |
| 5693547 | Method of making vertical MOSFET with sub-trench source contact | Mark I. Gardner | 1997-12-02 |
| 5686346 | Method for enhancing field oxide thickness at field oxide perimeters | — | 1997-11-11 |
| 5672531 | Method for fabrication of a non-symmetrical transistor | Mark I. Gardner, Derick J. Wristers | 1997-09-30 |
| 5145798 | Method of fabricating an insulated gate field effect transistor having lightly-doped source and drain extensions using an oxide sidewall spacer method | Michael C. Smayling | 1992-09-08 |
| 4677739 | High density CMOS integrated circuit manufacturing process | Robert Reid Doering, Gregory J. Armstrong | 1987-07-07 |
| 4569117 | Method of making integrated circuit with reduced narrow-width effect | David A. Baglee, Michael C. Smayling, Mamoru Itoh | 1986-02-11 |
| 4566175 | Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations | Michael C. Smayling | 1986-01-28 |