Issued Patents All Time
Showing 51–75 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5675161 | Channel accelerated tunneling electron cell, with a select region incorporated, for high density low power applications | — | 1997-10-07 |
| 5519653 | Channel accelerated carrier tunneling-(CACT) method for programming memories | — | 1996-05-21 |
| 5514884 | Very high density wafer scale device architecture | James W. Hively, Richard L. Bechtel | 1996-05-07 |
| 5506431 | Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications | — | 1996-04-09 |
| 5502315 | Electrically programmable interconnect structure having a PECVD amorphous silicon element | Hua-Thye Chua, Andrew K. Chan, John Birkner, Ralph G. Whitten, Richard L. Bechtel | 1996-03-26 |
| 5315130 | Very high density wafer scale device architecture | James W. Hively, Richard L. Bechtel | 1994-05-24 |
| 5252507 | Very high density wafer scale device architecture | James W. Hively, Richard L. Bechtel | 1993-10-12 |
| 5223741 | Package for an integrated circuit structure | Richard L. Bechtel, James W. Hively | 1993-06-29 |
| 5182632 | High density multichip package with interconnect structure and heatsink | Richard L. Bechtel, James W. Hively | 1993-01-26 |
| 4929992 | MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions | Matthew Weinberg | 1990-05-29 |
| 4922318 | Bipolar and MOS devices fabricated on same integrated circuit substrate | Matthew Weinberg | 1990-05-01 |
| 4808548 | Method of making bipolar and MOS devices on same integrated circuit substrate | Matthew Weinberg | 1989-02-28 |
| 4800171 | Method for making bipolar and CMOS integrated circuit structures | Ali A. Iranmanesh | 1989-01-24 |
| 4789760 | Via in a planarized dielectric and process for producing same | Linda Koyama, Harry J. Levinson | 1988-12-06 |
| 4707456 | Method of making a planar structure containing MOS and bipolar transistors | Matthew Weinberg | 1987-11-17 |
| 4696095 | Process for isolation using self-aligned diffusion process | — | 1987-09-29 |
| 4688314 | Method of making a planar MOS device in polysilicon | Matthew Weinberg | 1987-08-25 |
| 4686763 | Method of making a planar polysilicon bipolar device | Matthew Weinberg | 1987-08-18 |
| 4682409 | Fast bipolar transistor for integrated circuit structure and method for forming same | Matthew Weinberg | 1987-07-28 |
| 4672420 | Integrated circuit structure having conductive, protective layer for multilayer metallization to permit reworking | Yan Borodovsky, Danny Ma | 1987-06-09 |
| 4669180 | Method of forming emitter coupled logic bipolar memory cell using polysilicon Schottky diodes for coupling | Wen C. Ko | 1987-06-02 |
| 4669179 | Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions | Matthew Weinberg, Shiao H. Chang | 1987-06-02 |
| 4654824 | Emitter coupled logic bipolar memory cell | Wen C. Ko | 1987-03-31 |
| 4639288 | Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching | William L. Price, Ronald L. Schlupp | 1987-01-27 |
| 4635230 | Emitter coupled logic bipolar memory cell | Wen C. Ko | 1987-01-06 |