Issued Patents All Time
Showing 26–50 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10841227 | Network congestion and packet reordering | George Madathilparambil George, Susan George | 2020-11-17 |
| 10110498 | Networking using PCI express | George Madathilparambil George, Susan George | 2018-10-23 |
| 9749246 | Network congestion avoidance | George Madathilparambil George, Susan George | 2017-08-29 |
| 9554772 | Non-invasive imager for medical applications | Arun Mammen Thomas | 2017-01-31 |
| 9519608 | PCI express to PCI express based low latency interconnect scheme for clustering systems | — | 2016-12-13 |
| 9479442 | Method for congestion avoidance | George Madathilparambil George, Susan George | 2016-10-25 |
| 8811400 | Method for identifying next hop | George Madathilparambil George, Susan George | 2014-08-19 |
| 8189603 | PCI express to PCI express based low latency interconnect scheme for clustering systems | — | 2012-05-29 |
| 8139574 | Creation and transmission of part of protocol information corresponding to network packets or datalink frames separately | George Madathilparambil George, Susan George | 2012-03-20 |
| 7606248 | Method and apparatus for using multiple network processors to achieve higher performance networking applications | Greg Maturi, Neil Mammen, Sagar Edara | 2009-10-20 |
| 7583530 | Multi-bit memory technology (MMT) and cells | — | 2009-09-01 |
| 7376014 | Highly reliable NAND flash memory using five side enclosed floating gate storage elements | — | 2008-05-20 |
| 7339943 | Apparatus and method for queuing flow management between input, intermediate and output queues | Neil Mammen, Greg Maturi | 2008-03-04 |
| 7336669 | Mechanism for distributing statistics across multiple elements | Neil Mammen, Sagar Edara, Greg Maturi | 2008-02-26 |
| 7277437 | Packet classification method | Neil Mammen, Sanjay Agarwal, M. Varghese Ninan | 2007-10-02 |
| 7227786 | Location-specific NAND (LS NAND) memory technology and cells | — | 2007-06-05 |
| 7224620 | CAcT-Tg (CATT) low voltage NVM cells | — | 2007-05-29 |
| 7206857 | Method and apparatus for a network processor having an architecture that supports burst writes and/or reads | Neil Mammen, Greg Maturi | 2007-04-17 |
| 7193900 | CACT-TG (CATT) low voltage NVM cells | — | 2007-03-20 |
| 7149125 | Location-specific NAND (LS NAND) memory technology and cells | — | 2006-12-12 |
| 6150199 | Method for fabrication of programmable interconnect structure | Ralph G. Whitten, Richard L. Bechtel, Hua-Thye Chua, Andrew K. Chan, John Birkner | 2000-11-21 |
| 5989943 | Method for fabrication of programmable interconnect structure | Ralph G. Whitten, Richard L. Bechtel, Hua-Thye Chua, Andrew K. Chan, John Birkner | 1999-11-23 |
| 5780919 | Electrically programmable interconnect structure having a PECVD amorphous silicon element | Hua-Thye Chua, Andrew K. Chan, John Birkner, Ralph G. Whitten, Richard L. Bechtel | 1998-07-14 |
| 5717230 | Field programmable gate array having reproducible metal-to-metal amorphous silicon antifuses | Hua-Thye Chua, Andrew K. Chan, John Birkner, Ralph G. Whitten, Richard L. Bechtel | 1998-02-10 |
| 5691949 | Very high density wafer scale device architecture | James W. Hively, Richard L. Bechtel | 1997-11-25 |