Issued Patents All Time
Showing 26–50 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7174467 | Message based power management in a multi-processor system | Frank P. Helms, Dale E. Gulick, William A. Hughes, Paul C. Miranda, Derrick R. Meyer +2 more | 2007-02-06 |
| 7146510 | Use of a signal line to adjust width and/or frequency of a communication link during system operation | Frank P. Helms, Derrick R. Meyer, Dale E. Gulick, William A. Hughes, Scott E. Swanstrom | 2006-12-05 |
| 7051218 | Message based power management | Dale E. Gulick, Frank P. Helms, William A. Hughes, Paul C. Miranda, Derrick R. Meyer +2 more | 2006-05-23 |
| 7000149 | External loopback test mode | Veechoong “Jonas” Chia | 2006-02-14 |
| 6928528 | Guaranteed data synchronization | — | 2005-08-09 |
| 6865618 | System and method of assigning device numbers to I/O nodes of a computer system | Paul C. Miranda | 2005-03-08 |
| 6862647 | System and method for analyzing bus transactions | — | 2005-03-01 |
| 6857033 | I/O node for a computer system including an integrated graphics engine and an integrated I/O hub | Dale E. Gulick, James O. Mergard | 2005-02-15 |
| 6807599 | Computer system I/O node for connection serially in a chain to a host | Stephen C. Ennis | 2004-10-19 |
| 6791554 | I/O node for a computer system including an integrated graphics engine | James O. Mergard, Dale E. Gulick | 2004-09-14 |
| 6725297 | Peripheral interface circuit for an I/O node of a computer system | Tahsin Askar, Eric G. Chambers | 2004-04-20 |
| 6697890 | I/O node for a computer system including an integrated I/O interface | Dale E. Gulick | 2004-02-24 |
| 6618782 | Computer interconnection bus link layer | Dale E. Gulick, Alfred C. Hartmann, Geoffrey S. Strongin | 2003-09-09 |
| 6611891 | Computer resource configuration mechanism across a multi-pipe communication link | Dale E. Gulick | 2003-08-26 |
| 6571332 | Method and apparatus for combined transaction reordering and buffer management | Paul C. Miranda, Stephen C. Ennis | 2003-05-27 |
| 6557048 | Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof | James B. Keller, Derrick R. Meyer, Dale E. Gulick | 2003-04-29 |
| 6532019 | Input/output integrated circuit hub incorporating a RAMDAC | Dale E. Gulick | 2003-03-11 |
| 6389526 | Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system | James B. Keller, Dale E. Gulick, Geoffrey S. Strongin | 2002-05-14 |
| 6385705 | Circuit and method for maintaining order of memory access requests initiated by devices in a multiprocessor system | James B. Keller, Dale E. Gulick, Geoffrey S. Strongin | 2002-05-07 |
| 6370600 | Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency | William A. Hughes | 2002-04-09 |
| 6339808 | Address space conversion to retain software compatibility in new architectures | Greg Smaus | 2002-01-15 |
| 6272465 | Monolithic PC audio circuit | Jeffrey M. Blumenthal, Geoffrey E. Brehmer, Glen W. Brown, Carlin D. Cabler, Ryan Feemster +10 more | 2001-08-07 |
| 6253304 | Collation of interrupt control devices | David N. Suggs, Greg Smaus, Derrick R. Meyer | 2001-06-26 |
| 6202116 | Write only bus with whole and half bus mode operation | — | 2001-03-13 |
| 6199132 | Communication link with isochronous and asynchronous priority modes | Dale E. Gulick | 2001-03-06 |