SS

Scott E. Swanstrom

AM AMD: 23 patents #450 of 9,279Top 5%
Overall (All Time): #182,760 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11436114 Automatic part testing Amitabh Mehra, Anil Harwani, William Robert Alverson, Grant Evan Ley, Jerry Anton Ahrens +1 more 2022-09-06
11068368 Automatic part testing Amitabh Mehra, Anil Harwani, William Robert Alverson, Grant Evan Ley, Jerry Anton Ahrens +1 more 2021-07-20
7231474 Serial interface having a read temperature command Frank P. Helms, Larry D. Hewitt, Ross Voigt LaFetra 2007-06-12
7174467 Message based power management in a multi-processor system Frank P. Helms, Dale E. Gulick, Larry D. Hewitt, William A. Hughes, Paul C. Miranda +2 more 2007-02-06
7146510 Use of a signal line to adjust width and/or frequency of a communication link during system operation Frank P. Helms, Derrick R. Meyer, Larry D. Hewitt, Dale E. Gulick, William A. Hughes 2006-12-05
7051218 Message based power management Dale E. Gulick, Frank P. Helms, Larry D. Hewitt, William A. Hughes, Paul C. Miranda +2 more 2006-05-23
6061756 Computer system which performs intelligent byte slicing/data packing on a multi-byte wide bus Drew J. Dutton, J. Andrew Lambrecht 2000-05-09
6047350 Computer system which performs intelligent byte slicing on a multi-byte wide bus Drew J. Dutton, J. Andrew Lambrecht 2000-04-04
6035364 Independent use of bits on an on-chip bus J. Andrew Lambrecht 2000-03-07
5964859 Allocatable post and prefetch buffers for bus bridges Andy Steinbach, Michael T. Wisor 1999-10-12
5956493 Bus arbiter including programmable request latency counters for varying arbitration priority Larry D. Hewitt 1999-09-21
5948093 Microprocessor including an interrupt polling unit configured to poll external devices for interrupts when said microprocessor is in a task switch state David S. Christie, Steven L. Belt 1999-09-07
5920891 Architecture and method for controlling a cache memory Andy Steinbach, Michael T. Wisor 1999-07-06
5872942 Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent byte slicing Steven L. Belt 1999-02-16
5822568 System for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller 1998-10-13
5790815 Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent byte slicing Steven L. Belt 1998-08-04
5754884 Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller 1998-05-19
5754801 Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent data transfers Andy Lambrecht, Drew J. Dutton 1998-05-19
5687381 Microprocessor including an interrupt polling unit configured to poll external devices for interrupts using interrupt acknowledge bus transactions David S. Christie, Steven L. Belt 1997-11-11
5668977 Dockable computer system capable of electric and electromagnetic communication Douglas D. Gephardt 1997-09-16
5632020 System for docking a portable computer to a host computer without suspending processor operation by a docking agent driving the bus inactive during docking Douglas D. Gephardt 1997-05-20
5598539 Apparatus and method for achieving hot docking capabilities for a dockable computer system Douglas D. Gephardt 1997-01-28
5598537 Apparatus and method for driving a bus to a docking safe state in a dockable computer system including a docking station and a portable computer Douglas D. Gephardt 1997-01-28