Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6857033 | I/O node for a computer system including an integrated graphics engine and an integrated I/O hub | Dale E. Gulick, Larry D. Hewitt | 2005-02-15 |
| 6791554 | I/O node for a computer system including an integrated graphics engine | Dale E. Gulick, Larry D. Hewitt | 2004-09-14 |
| 6625683 | Automatic early PCI transaction retry | Asif Khan | 2003-09-23 |
| 6484227 | Method and apparatus for overlapping programmable address regions | Michael S. Quimby | 2002-11-19 |
| 6415348 | Flexible microcontroller architecture | James R. Magro, Michael S. Quimby, Pratik M. Mehta | 2002-07-02 |
| 6401156 | Flexible PC/AT-compatible microcontroller | James R. Magro, Michael S. Quimby, Pratik M. Mehta | 2002-06-04 |
| 6163826 | Method and apparatus for non-concurrent arbitration of multiple busses | Asif Khan | 2000-12-19 |
| 6009489 | Method and system for supporting non-deterministic burst lengths in a memory system employing extended data out(EDO)DRAM | — | 1999-12-28 |
| 5996051 | Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a second mode supports non-concurrent memory accesses to the entire memory array | — | 1999-11-30 |
| 5941968 | Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device | Michael S. Quimby, Carl K. Wakeland | 1999-08-24 |
| 5897659 | Modifying RAS timing based on wait states to accommodate different speed grade DRAMs | Robert Paul Gittinger | 1999-04-27 |
| 5881248 | System and method for optimizing system bus bandwidth in an embedded communication system | — | 1999-03-09 |