Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10110202 | Distributed voltage and temperature compensation for clock deskewing | John O'Dwyer | 2018-10-23 |
| 10043724 | Using an integrated circuit die for multiple devices | Nui Chong | 2018-08-07 |
| 9859896 | Distributed multi-die routing in a multi-chip module | Steven P. Young, Eric F. Dellinger | 2018-01-02 |
| 9602108 | Lut cascading circuit | Steven P. Young, Alireza S. Kaviani | 2017-03-21 |
| 9559669 | Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit | — | 2017-01-31 |
| 9509307 | Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer | Vikram Santurkar, Anil Kumar Kandala, Santosh Yachareni, Shidong Zhou, Robert Fu +3 more | 2016-11-29 |
| 9496871 | Programmable power reduction technique using transistor threshold drops | Benjamin S. Devlin, Santosh Kumar Sood | 2016-11-15 |
| 9455714 | Cascaded LUT carry logic circuit | — | 2016-09-27 |
| 9438244 | Circuits for and methods of controlling power within an integrated circuit | Santosh Kumar Sood, Steven P. Young | 2016-09-06 |
| 9411554 | Signed multiplier circuit utilizing a uniform array of logic blocks | Steven P. Young | 2016-08-09 |
| 9143122 | Adaptive low skew clocking architecture | — | 2015-09-22 |
| 9007110 | Register circuits and methods of storing data in a register circuit | — | 2015-04-14 |
| 9002915 | Circuits for shifting bussed data | Steven P. Young | 2015-04-07 |
| 8937491 | Clock network architecture | Steven P. Young, Trevor J. Bauer, Robert M. Ondris, Dinesh D. Gaitonde | 2015-01-20 |
| 8933447 | Method and apparatus for programmable device testing in stacked die applications | Arifur Rahman, Ramakrishna K. Tanikella, Trevor J. Bauer, Steven P. Young | 2015-01-13 |
| 8928386 | Circuits for and methods of asychronously transmitting data in an integrated circuit | Ilya K. Ganusov | 2015-01-06 |
| 8893071 | Methods of pipelining a data path in an integrated circuit | — | 2014-11-18 |
| 8866509 | Flip-flop array with option to ignore control signals | Robert Fu, Chi M. Nguyen, James M. Simkins, Brian D. Philoksky | 2014-10-21 |
| 8773164 | Programmable interconnect network | Steven P. Young | 2014-07-08 |
| 8773166 | Self-timed single track circuit | Steven P. Young | 2014-07-08 |
| 8536895 | Configuration of a multi-die integrated circuit | Weiguang Lu, Eric E. Edwards, Paul-Hugo Lamarche, Steven P. Young, Joe Eddie Leyba, II | 2013-09-17 |
| 8527572 | Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same | Steven P. Young | 2013-09-03 |
| 8058897 | Configuration of a multi-die integrated circuit | Weiguang Lu, Eric E. Edwards, Paul-Hugo Lamarche, Steven P. Young, Joe Eddie Leyba, II | 2011-11-15 |
| 7948265 | Circuits for replicating self-timed logic | Steven P. Young | 2011-05-24 |
| 7746102 | Bus-based logic blocks for self-timed integrated circuits | Steven P. Young | 2010-06-29 |